3D floorplanning considering vertically aligned rectilinear modules using T∗-tree

Three-dimensional integrated circuits gain more and more attention due to their benefits in wirelength reduction and their potential for heterogeneous integration of systems on a chip. Besides the advantages they also lead to new challenges and increasing complexity in designing such systems. This paper focuses on floorplanning such systems. It describes a new data structure called T*-tree which enables the design of three-dimensional integrated circuits considering vertically aligned rectilinear 2D modules. The problem formulation of the new T*-tree differs from the T-tree proposed in [1]. Furthermore, an optimization algorithm is presented which is aware of fixed-outline constraints using a longest path based method. Experimental results show that the T*-tree is competitive to other approaches. It is also able to consider more appropriate modules for three-dimensional integration.

[1]  Yao-Wen Chang,et al.  Arbitrarily shaped rectilinear module placement using the transitive closure graph representation , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Jason Cong,et al.  Fine grain 3D integration for microarchitecture design through cube packing exploration , 2007, 2007 25th International Conference on Computer Design.

[3]  Yao-Wen Chang,et al.  Rectilinear block placement using B*-trees , 2000, Proceedings 2000 International Conference on Computer Design.

[4]  Hiroshi Murata,et al.  Arbitrary convex and concave rectilinear block packing using sequence-pair , 1999, ISPD '99.

[5]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[6]  Yao-Wen Chang,et al.  B*-trees: a new representation for non-slicing floorplans , 2000, Proceedings 37th Design Automation Conference.

[7]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Yici Cai,et al.  Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on corner block list , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Yici Cai,et al.  Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Yoji Kajitani,et al.  Module placement on BSG-structure with pre-placed modules and rectilinear modules , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

[11]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.

[12]  Yao-Wen Chang,et al.  Temporal floorplanning using the T-tree formulation , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[13]  Malgorzata Chrzanowska-Jeske,et al.  Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.