论文信息 - A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 /spl mu/m CMOS

A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 /spl mu/m CMOS

A completely integrated 4:1 multiplexer for high speed operation and low power consumption in 0.13 /spl mu/m CMOS is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with 25% duty cycle select inputs to appear at the MUX-output. The lower number of gates enables low power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The MUX works from DC up to 20 Gb/s and consumes 82 mW.

H.-D. Wohlmuth | D. Kehrer

[1] M. Wurzer,et al. 40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[2] G. Knoblinger,et al. A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).