Novel structures for serial multiplication over the finite field GF(2/sup m/)
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[1] Cheng-Wen Wu,et al. Bit-level systolic arrays for finite-field multiplications , 1995, J. VLSI Signal Process..
[2] Eiji Fujiwara,et al. Error-control coding for computer systems , 1989 .
[3] Trieu-Kien Truong,et al. Systolic Multipliers for Finite Fields GF(2m) , 1984, IEEE Transactions on Computers.
[4] Ke Wang,et al. The VLSI Implementation of a Reed—Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm , 1984, IEEE Transactions on Computers.
[5] Chin-Liang Wang,et al. Systolic array implementation of multipliers for finite fields GF(2/sup m/) , 1991 .
[6] Trieu-Kien Truong,et al. A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases , 1988, IEEE Trans. Computers.
[7] Trieu-Kien Truong,et al. VLSI Architectures for Computing Multiplications and Inverses in GF(2m) , 1983, IEEE Transactions on Computers.
[8] Keshab K. Parhi,et al. A Fast Radix-4 Division Algorithm and Its Architecture , 1995, IEEE Trans. Computers.
[9] Vijay K. Bhargava,et al. Division and bit-serial multiplication over GF(qm) , 1992 .
[10] Dorothy E. Denning,et al. Cryptography and Data Security , 1982 .