Introduction to High-Level Synthesis

Advanced microelectronic capabilities are widely regarded as essential for an advanced industrial base. Very Large Scale Integration (VLSI) circuits are used ubiquitously in industrial products, and are critical to the progress of many fields. The competitiveness of the electronic industry requires ever-decreasing design and fabrication times for increasingly complex circuits. In addition, higher circuit speeds, close to zero defects, high yields, and application-specific integrated circuits (ASICs) produced in smaller volumes are further stressing the limits of design and fabrication. In the design of digital circuits in particulardesign automation(DA) has been instrumental in achieving these goals.

[1]  Alexandru Nicolau,et al.  Percolation Scheduling: A Parallel Compilation Technique , 1985 .

[2]  Wolfgang Rosenstiel.  Optimizations in high level synthesis , 1986 .

[3]  Giovanni De Micheli,et al.  Partitioning of functional models of synchronous digital systems , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  Nikil D. Dutt,et al.  An intermediate representation for behavioral synthesis , 1991, DAC '90.

[5]  Raul Camposano,et al.  Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Alice C. Parker,et al.  Tutorial on high-level synthesis , 1988, DAC '88.

[7]  Howard Trickey,et al.  Flamel: A High-Level Hardware Compiler , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Donald E. Thomas,et al.  Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench , 1989 .

[9]  Reinaldo A. Bergamaschi,et al.  Area and performance optimizations in path-based scheduling , 1991, Proceedings of the European Conference on Design Automation..

[10]  Reinaldo A. Bergamaschi,et al.  Redesign using state splitting , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[11]  Alice C. Parker,et al.  A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  John Cocke,et al.  A methodology for the real world , 1981 .

[13]  Alice C. Parker,et al.  MAHA: A Program for Datapath Synthesis , 1986, DAC 1986.

[14]  Donald E. Thomas,et al.  Architectural Partitioning for System Level Design , 1989, 26th ACM/IEEE Design Automation Conference.

[15]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Wolfgang Rosenstiel,et al.  Synthesizing circuits from behavioural descriptions , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Ahmed Hemani,et al.  A neural net based self organising scheduling algorithm , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[18]  Srinivas Devadas,et al.  Algorithms for hardware allocation in data path synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Zebo Peng.  Synthesis of VLSI Systems with the CAMAD Design Aid , 1986, DAC 1986.

[20]  Pierre G. Paulin,et al.  Force-Directed Scheduling in Automatic Data Path Synthesis , 1987, 24th ACM/IEEE Design Automation Conference.

[21]  R. Composano,et al.  Path-based scheduling for synthesis , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[22]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[23]  M.C. McFarland.  Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions , 1986, 23rd ACM/IEEE Design Automation Conference.

[24]  Nohbyung Park,et al.  SEHWA: A Program for Synthesis of Pipelines , 1986, 23rd ACM/IEEE Design Automation Conference.

[25]  Allen Newell,et al.  Computer Structures: Readings and Examples, , 1971 .

[26]  Donald E. Thomas,et al.  The combination of scheduling, allocation, and mapping in a single algorithm , 1991, DAC '90.

[27]  Daniel Gajski,et al.  New VLSI Tools - Guest Editors' Introduction , 1983, Computer.

[28]  Gaetano Borriello.  Combining event and data-flow graphs in behavioral synthesis , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[29]  Fadi J. Kurdahi,et al.  REAL: A Program for REgister ALlocation , 1987, 24th ACM/IEEE Design Automation Conference.

[30]  Youn-Long Lin,et al.  A new integer linear programming formulation for the scheduling problem in data path synthesis , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[31]  Alexandru Nicolau,et al.  Percolation based synthesis , 1991, DAC '90.

[32]  V. Berstis.  The V compiler: automatic hardware design , 1989, IEEE Design & Test of Computers.

[33]  Arun K. Majumdar,et al.  Allocation of multiport memories in data path synthesis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  Ajoy K. Bose,et al.  Bridge: a versatile behavioral synthesis system , 1988, DAC '88.

[35]  Mohamed I. Elmasry,et al.  Global optimization approach for architectural synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Michael C. McFarland,et al.  Incorporating bottom-up design into hardware synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[37]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[38]  Gajski,et al.  Guest Editors' Introduction: New VLSI Tools , 1983, Computer.

[39]  Bruce D. Shriver,et al.  Some Experiments in Local Microcode Compaction for Horizontal Machines , 1981, IEEE Transactions on Computers.

[40]  Daniel Gajski,et al.  Design Tools for Intelligent Silicon Compilation , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[41]  Daniel P. Siewiorek,et al.  Automated Synthesis of Data Paths in Digital Systems , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[42]  Donald E. Thomas,et al.  Behavioral transformation for algorithmic level IC design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[43]  Raul Camposano.  From behavior to structure: high-level synthesis , 1990, IEEE Design & Test of Computers.

[44]  Kazutoshi Wakabayashi,et al.  A resource sharing and control synthesis method for conditional branches , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[45]  S. J. McFarland,et al.  The value trace : a data base for automated digital design , 1978 .

[46]  Alice C. Parker,et al.  Register-Transfer Level Digital Design Automation: The Allocation Process , 1978, 15th Design Automation Conference.

[47]  Thaddeus J. Kowalski.  An artificial intelligence approach to VLSI design , 1985 .