Pulsed-Latch Utilization for Clock-Tree Power Optimization

Minimizing the size of a clock tree is known as an effective approach to reduce power dissipation in modern circuit designs. However, most existing power-aware clock-tree minimization algorithms optimize power on the basis of flip-flops alone, which may result in limited power savings. To achieve a power and timing tradeoff, this paper investigates the pulsed-latch utilization in a clock tree for further power savings. This is the first paper to propose a migration approach to efficiently construct a clock tree with both pulsed-latches and flip-flops. The proposed method is based on minimum-cost maximum-flow formulation to globally determine the tree topology, which maintains load balance and considers the wirelength between pulse generators and pulsed latches. Experimental results indicate that the proposed migration approach can improve the power consumption by 12% and 13% with 7% and 70% skew improvements on average compared with the most recent paper on the industrial circuits and ISPD-2010 benchmarks, respectively.

[1]  Masato Edahiro,et al.  A Clustering-Based Optimization Algorithm in Zero-Skew Routings , 1993, 30th ACM/IEEE Design Automation Conference.

[2]  Youngsoo Shin,et al.  Clock Gating Synthesis of Pulsed-Latch Circuits , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Sachin S. Sapatnekar,et al.  Low-power clock distribution using multiple voltages and reduced swings , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Hyein Lee,et al.  Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Youngsoo Shin,et al.  Pulser gating: A clock gating of pulsed-latch circuits , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[6]  Massoud Pedram,et al.  Gated clock routing for low-power microprocessor design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Tsung-Yi Ho,et al.  Pulsed-latch-based clock tree migration for dynamic power reduction , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[8]  Chia-Chun Tsai,et al.  Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs , 2012, TODE.

[9]  Youngsoo Shin,et al.  Pulsed-latch circuits to push the envelope of ASIC design , 2010, 2010 International SoC Design Conference.

[10]  Mark Horowitz,et al.  Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.

[11]  Gi-Joon Nam,et al.  Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Wenting Hou,et al.  Automatic register banking for low-power clock trees , 2009, 2009 10th International Symposium on Quality Electronic Design.

[13]  Steven Fortune,et al.  A sweepline algorithm for Voronoi diagrams , 1986, SCG '86.

[14]  Yao-Wen Chang,et al.  Pulsed-Latch Aware Placement for Timing-Integrity Optimization , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Massoud Pedram,et al.  Clock-gating and its application to low power design of sequential circuits , 2000 .

[16]  Sunil P. Khatri,et al.  A robust, fast pulsed flip-flop design , 2008, GLSVLSI '08.

[17]  Ankur Srivastava,et al.  Activity-driven clock design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  F. Weber,et al.  Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[19]  Rupesh S. Shelar.  An efficent clustering algorithm for low power clock tree synthesis , 2007, ISPD '07.