A Comprehensive Crossbar Array Model With Solutions for Line Resistance and Nonlinear Device Characteristics
暂无分享,去创建一个
[1] U-In Chung,et al. Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications , 2006, 2009 Symposium on VLSI Technology.
[2] Sasago Yoshitaka,et al. Cross-Point phase change memory with 4F2 cell size driven by low-contact resistivity poly-si diode , 2009 .
[3] Rainer Waser,et al. Complementary resistive switches for passive nanocrossbar memories. , 2010, Nature materials.
[4] T.G. Noll,et al. Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.
[5] Adam C. Cabe,et al. Design approaches for hybrid CMOS/molecular memory based on experimental device data , 2006, GLSVLSI '06.
[6] Seth Copen Goldstein,et al. Molecular electronics: from devices and interconnect to circuits and architecture , 2003, Proc. IEEE.
[7] Cheol Seong Hwang,et al. A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory , 2010, Nanotechnology.
[8] I. Yoo,et al. 2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications , 2007, 2007 IEEE International Electron Devices Meeting.
[9] Wei Yang Lu,et al. Nanoscale memristor device as synapse in neuromorphic systems. , 2010, Nano letters.
[10] Mircea R. Stan,et al. Design and analysis of crossbar circuits for molecular nanoelectronics , 2002, Proceedings of the 2nd IEEE Conference on Nanotechnology.
[11] S. Hamdioui,et al. Emerging crossbar-based hybrid nanoarchitectures for future computing systems , 2008, 2008 2nd International Conference on Signals, Circuits and Systems.
[12] Paul D Franzon,et al. Scaling constraints in nanoelectronic random-access memories , 2005, Nanotechnology.
[13] R. Waser,et al. A Fundamental Analysis of Nano-Crossbars with Non-Linear Switching Materials and its Impact on TiO2 as a Resistive Layer , 2008, 2008 8th IEEE Conference on Nanotechnology.
[14] Yi-Chou Chen,et al. An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device , 2003, IEEE International Electron Devices Meeting 2003.
[15] H.-S. Philip Wong,et al. Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters , 2010, 2010 IEEE International Interconnect Technology Conference.
[16] Jiale Liang,et al. Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective , 2012, 2012 4th IEEE International Memory Workshop.
[17] P. Lugli,et al. Read-Out Design Rules for Molecular Crossbar Architectures , 2009, IEEE Transactions on Nanotechnology.