Investigation of overlay errors due to the interaction of optical and extreme ultraviolet mask fabrication processes

Overlay tolerances are becoming increasingly severe as lithography technology drives the minimum integrated-circuit feature size below 65nm. Manufacturable solutions at the lower nodes are essentially unknown. The goal of this article is to investigate overlay errors at the 45-nm node, for a mix-and-match of optical and extreme ultraviolet (EUV) lithographies. In particular, image placement errors induced during mask fabrication are predicted for a specified test pattern, which includes the possibility of having individual layers on the device wafer patterned by either optical or EUV lithographic processes. Finite element (FE) models have been developed to simulate the response of both optical and EUV masks during fabrication and chucking. In order to track image placement errors of the actual features within the pattern area, submodeling techniques were developed for the FE simulations. In addition, equivalent material properties were determined for the individual patterns used for the different optical ...