论文信息 - An 8-bit, 200 MSPS Folding and Interpolating ADC

An 8-bit, 200 MSPS Folding and Interpolating ADC

An 8-bit, 200 MSPS folding and interpolating analog-to-digitalconverter, ADC, has been implemented in a 1.2 µmBiCMOS-process. It achieves 7.5 effective bits with a power dissipationof 575mW. The active area is 4mm2. The implementationand measured results are presented. A simple analytical modelfor the interpolation-induced nonlinearity in a folding and interpolatingADC using sinusoidal folding is presented. The bowing of thereference ladder due to interaction with the input stages isanalyzed, and analytical models are derived.

Geir S. Østrem | Øystein Moldsvor

[1] J. Doernberg,et al. Full-speed testing of A/D converters , 1984 .

[2] R. van de Grift,et al. An 8-bit video ADC incorporating folding and interpolation techniques , 1987 .

[3] Akira Matsuzawa,et al. A 10-b 300-MHz interpolated-parallel A/D converter , 1993 .

[4] B. Zojer,et al. A 6-Bit/200-MHz Full Nyquist A/D Converter , 1985, IEEE Journal of Solid-State Circuits.

[5] R. J. van de Plassche,et al. An 8-b 650-MHz folding ADC , 1992 .

[6] Peter Baltus,et al. An 8-bit 100-MHz full-Nyquist analog-to-digital converter , 1988 .