Carleton’s HAL System

The HAL (Hardware Allocator) system was Paulin’s thesis work at Carleton University. HAL includes scheduling, data path synthesis, and design iteration.

[1]  Pierre G. Paulin,et al.  Scheduling and Binding Algorithms for High-Level Synthesis , 1989, 26th ACM/IEEE Design Automation Conference.

[2]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Pierre Gaston Paulin.  High-level synthesis of digital circuits using global scheduling and binding algorithms , 1988 .

[4]  Pierre G. Paulin,et al.  Force-Directed Scheduling in Automatic Data Path Synthesis , 1987, 24th ACM/IEEE Design Automation Conference.

[5]  P.G. Paulin,et al.  Algorithms for high-level synthesis , 1989, IEEE Design & Test of Computers.

[6]  E. F. Girczyc,et al.  HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis , 1986, 23rd ACM/IEEE Design Automation Conference.