All-digital built-in self-test scheme for charge-pump phase-locked loops

[1]  Jacob A. Abraham,et al.  PLL lock time prediction and parametric testing by lock waveform characterization , 2010, 2010 IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW).

[2]  Abhijit Chatterjee,et al.  Analog Sensor Based Testing of Phase-Locked Loop Dynamic Performance Parameters , 2013, 2013 22nd Asian Test Symposium.

[3]  Stephen K. Sunter,et al.  Experiences with parametric BIST for production testing PLLs with picosecond precision , 2010, 2010 IEEE International Test Conference.

[4]  J. A. Abraham,et al.  Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources , 2012, 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop.

[5]  M. Soma,et al.  Challenges in analog and mixed-signal fault models , 1996 .

[6]  Mohamed Masmoudi,et al.  High Performance BIST PLL approach for VCO testing , 2014, 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP).

[7]  Alvin Leng Sun Loke,et al.  An Embedded All-Digital Circuit to Measure PLL Response , 2010, IEEE Journal of Solid-State Circuits.

[8]  Weiwei Shan,et al.  On-chip long-term jitter measurement for PLL based on undersampling technique , 2013, IEICE Electron. Express.

[9]  Meng Zhang,et al.  Built-in self-test structure for fault detection of charge-pump phase-locked loop , 2016, IET Circuits Devices Syst..

[10]  Jen-Chieh Liu,et al.  Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  A. Tiwari,et al.  An innovative approach of computational fault detection using design for testability of CP-PLL , 2012, 2012 NATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION SYSTEMS.

[12]  Meng Zhang,et al.  A low-cost built-in self-test for CP-PLL based on TDC , 2014, IEICE Electron. Express.

[13]  Jaeha Kim,et al.  On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Joseph Kho,et al.  An enhanced high-precision and time-saving jitter transfer measurement , 2009, 2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS).

[15]  Wenceslas Rahajandraibe,et al.  Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Gordon W. Roberts,et al.  Reducing measurement uncertainty in a DSP-based mixed-signal test environment without increasing test time , 2004, 2004 International Conferce on Test.

[17]  Linda S. Milor,et al.  A BIST Circuit for DLL Fault Detection , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Salvatore Levantino,et al.  Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Yi-Ting Lai,et al.  Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application , 2009, IEEE Transactions on Instrumentation and Measurement.

[20]  Bharadwaj Amrutur,et al.  0.84 ps Resolution Clock Skew Measurement via Subsampling , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.