VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/)

A systolic power-sum circuit designed to perform AB/sup 2/+C computation in the finite field GF(2/sup m/) has been presented recently. Based on the power-sum circuit, a VLSI architecture for performing exponentiations in GF(2/sup m/) is developed. Furthermore, two modified architectures that can be used to compute multiplicative inverses and divisions in GF(2/sup m/) are proposed respectively. All the architectures are constructed by m-1 power-sum circuits. The average computation time of the architectures is only two logic gate delays and the circuit complexity is realizable in present VLSI technology. It should be emphasized at this point that the computation time of two gate delays is the highest computation speed in finite field arithmetic.<<ETX>>