3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions
暂无分享,去创建一个
Min Chul Sung | Sukhan Lee | Kiwon Lee | Mohammad Alian | Chankyung Kim | Wooyeong Cho | Reum Oh | O Seongil | Jung Ho Ahn | Nam Sung Kim | N. Kim | Mohammad Alian | Reum Oh | O. Seongil | Sukhan Lee | Kiwon Lee | Min Chul Sung | Chankyung Kim | Wooyeong Cho
[1] A. Jaleel. Memory Characterization of Workloads Using Instrumentation-Driven Simulation A Pin-based Memory Characterization of the SPEC CPU 2000 and SPEC CPU 2006 Benchmark Suites , 2022 .
[2] Joonyoung Kim,et al. HBM: Memory solution for bandwidth-hungry processors , 2014, 2014 IEEE Hot Chips 26 Symposium (HCS).
[3] Onur Mutlu,et al. Simultaneous Multi-Layer Access , 2016, ACM Trans. Archit. Code Optim..
[4] Mohammad Alian,et al. dist-gem5: Distributed simulation of computer clusters , 2017, 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).
[5] Yuan Xie,et al. Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.
[6] Christoforos E. Kozyrakis,et al. Memory Hierarchy for Web Search , 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[7] Mattan Erez,et al. Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).
[8] Doubletree Hotel San Jose,et al. The World's Most Popular Open Source Database , 2003 .
[9] Seok-Hee Lee,et al. Technology scaling challenges and opportunities of memory devices , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).
[10] O Seongil,et al. Reducing memory access latency with asymmetric DRAM bank organizations , 2013, ISCA.
[11] J. M. Park,et al. 20nm DRAM: A new beginning of another revolution , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).
[12] Sukhan Lee,et al. CiDRA: A cache-inspired DRAM resilience architecture , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).
[13] Onur Mutlu,et al. Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.
[14] Mark D. Hill,et al. Efficiently enabling conventional block sizes for very large die-stacked DRAM caches , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[15] Daniel Sánchez,et al. Tailbench: a benchmark suite and evaluation methodology for latency-critical applications , 2016, 2016 IEEE International Symposium on Workload Characterization (IISWC).
[16] Tao Zhang,et al. Overcoming the challenges of crossbar resistive memory architectures , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).
[17] Reum Oh,et al. Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.
[18] Onur Mutlu,et al. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems , 2008, 2008 International Symposium on Computer Architecture.
[19] Brad Calder,et al. Automatically characterizing large scale program behavior , 2002, ASPLOS X.
[20] Norman P. Jouppi,et al. Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[21] J. Thomas Pawlowski,et al. Hybrid memory cube (HMC) , 2011, 2011 IEEE Hot Chips 23 Symposium (HCS).
[22] Ricardo Bianchini,et al. Page placement in hybrid memory systems , 2011, ICS '11.
[23] Onur Mutlu,et al. Tiered-latency DRAM: A low latency and low cost DRAM architecture , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).
[24] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[25] O Seongil,et al. Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[26] Wongyu Shin,et al. NUAT: A non-uniform access time memory controller , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).
[27] Anoop Gupta,et al. The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.
[28] Rachata Ausavarungnirun,et al. RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[29] Sukhan Lee,et al. Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices , 2018, IEEE Access.
[30] Jung Ho Ahn,et al. CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[31] Kai Li,et al. PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors , 2008, 2008 IEEE International Symposium on Workload Characterization.
[32] Florence March,et al. 2016 , 2016, Affair of the Heart.
[33] Aamer Jaleel,et al. CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[34] Jung Ho Ahn,et al. Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[35] Yan Solihin,et al. CHOP: Integrating DRAM Caches for CMP Server Platforms , 2011, IEEE Micro.
[36] Yuan Xie,et al. Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[37] Alaa R. Alameldeen,et al. Transparent Hardware Management of Stacked DRAM as Part of Memory , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[38] Norman P. Jouppi,et al. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[39] A. James. 2010 , 2011, Philo of Alexandria: an Annotated Bibliography 2007-2016.
[40] Dae-Hyun Kim,et al. ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates , 2013, ISCA.
[41] Avinash Sodani,et al. Knights landing (KNL): 2nd Generation Intel® Xeon Phi processor , 2015, 2015 IEEE Hot Chips 27 Symposium (HCS).
[42] O Seongil,et al. McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).
[43] Reena Panda,et al. SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization , 2016, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[44] Onur Mutlu,et al. Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[45] Moinuddin K. Qureshi,et al. XED: Exposing On-Die Error Detection Information for Strong Memory Reliability , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).
[46] Tajana Simunic,et al. PDRAM: A hybrid PRAM and DRAM main memory system , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[47] A. Azzouz. 2011 , 2020, City.
[48] Vijayalakshmi Srinivasan,et al. Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.
[49] Varsha Apte,et al. A Measurement Study of the Linux TCP/IP Stack Performance and Scalability on SMP systems , 2006, 2006 1st International Conference on Communication Systems Software & Middleware.
[50] Jongman Kim,et al. An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).
[51] Onur Mutlu,et al. Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management , 2012, IEEE Computer Architecture Letters.