Delay models for verifying speed-dependent asynchronous circuits

It is demonstrated that the binary inertial delay model can lead to false positive results when used in the verification of speed-dependent asynchronous circuits. A delay model called the binary chaos delay model solves this problem in many cases. The two timing models are compared by using them in the verification of a FIFO controller circuit. The models can be viewed as two extremes of a more general, parameterized model.<<ETX>>

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