Analog MOS Vector Multipliers for the Implementation of Synapses in Artificial Neural Networks

All-MOS analog vector-vector multipliers are described and designed for the implementation of the linear multiplication between analog signals and analog synaptic weights in artificial neural networks (ANNs). Employing these multipliers, large-scale artificial neural networks can be implemented using fewer MOS transistors than are required by implementations employing the so-called Gilbert multiplier. PSPICE circuit simulations have been extensively executed in order to quantify the performance of these multipliers by measuring the following specifications: maximum percentage error, output offset, X or Y nonlinearity, X or Y feedthrough, small-signal bandwidth, and slew rate. An 11-dimensional analog vector multiplier has been designed on a 40-pin MOSIS TINYCHIP with analog pads using the MAGIC VLSI tools and has been fabricated using 2 μm CMOS n-well process via MOSIS.