Multiple Gate Field-Effect Transistors for Future CMOS Technologies
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[1] Y. Yeo,et al. 25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.
[2] Tzuen-Hsi Huang,et al. Back-gate forward bias method for low-voltage CMOS digital circuits , 1996 .
[3] Ying Zhang,et al. Extension and source/drain design for high-performance FinFET devices , 2003 .
[4] H.-S. Philip Wong. Beyond the conventional transistor , 2002, IBM J. Res. Dev..
[5] C. Hu,et al. Nanoscale CMOS spacer FinFET for the terabit era , 2002 .
[6] H. Wong,et al. CMOS scaling into the nanometer regime , 1997, Proc. IEEE.
[7] H.-S.P. Wong,et al. Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[8] R. Rooyackers,et al. Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency , 2006, 2006 International Electron Devices Meeting.
[9] Edward J. Nowak,et al. Maintaining the benefits of CMOS scaling when scaling bogs down , 2002, IBM J. Res. Dev..
[10] R. Rooyackers,et al. Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions , 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..
[11] A.P. Johnson,et al. A sub 40-nm body thickness n-type FinFET , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).
[12] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs , 2004 .
[13] D. Hisamoto,et al. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET , 1990, IEEE Electron Device Letters.
[14] Joachim Keinert,et al. Scaling beyond the 65 nm node with FinFET-DGCMOS , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[15] Chenming Hu,et al. Sub-60-nm quasi-planar FinFETs fabricated using a simplified process , 2001, IEEE Electron Device Letters.
[16] D. Hisamoto. FD/DG-SOI MOSFET-a viable approach to overcoming the device scaling limit , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[17] E. Nowak,et al. High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[18] R. Rooyackers,et al. Integration challenges for multi-gate devices , 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..
[19] N. Collaert,et al. Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.
[20] Chenming Hu,et al. Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[21] J. Bokor,et al. A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation , 1994, IEEE Electron Device Letters.
[22] C. Hu,et al. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .
[23] C. Hu,et al. A spacer patterning technology for nanoscale CMOS , 2002 .
[24] Bin Yu,et al. FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.
[25] Jong-Ho Lee,et al. Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[26] Chenming Hu,et al. Spacer FinFET: nano-scale CMOS technology for the terabit era , 2001, 2001 International Semiconductor Device Research Symposium. Symposium Proceedings (Cat. No.01EX497).
[27] David J. Frank,et al. Nanoscale CMOS , 1999, Proc. IEEE.
[28] Jeffrey Bokor,et al. Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.
[29] P. Kinget,et al. 0.5-V analog circuit techniques and their application in OTA and filter design , 2005, IEEE Journal of Solid-State Circuits.
[30] T. Skotnicki,et al. The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance , 2005, IEEE Circuits and Devices Magazine.