Memristive Mixed-Signal Neuromorphic Systems: Energy-Efficient Learning at the Circuit-Level

Neuromorphic computing is non-von Neumann computer architecture for the post Moore’s law era of computing. Since a main focus of the post Moore’s law era is energy-efficient computing with fewer resources and less area, neuromorphic computing contributes effectively in this research. In this paper, we present a memristive neuromorphic system for improved power and area efficiency. Our particular mixed-signal approach implements neural networks with spiking events in a synchronous way. Moreover, the use of nano-scale memristive devices saves both area and power in the system. We also provide device-level considerations that make the system more energy-efficient. The proposed system additionally includes synchronous digital long term plasticity, an online learning methodology that helps the system train the neural networks during the operation phase and improves the efficiency in learning considering the power consumption and area overhead.

[1]  Catherine D. Schuman,et al.  An evolutionary optimization framework for neural networks and neuromorphic architectures , 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

[2]  Farnood Merrikh-Bayat,et al.  Efficient training algorithms for neural networks based on memristive crossbar circuits , 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

[3]  Dhireesha Kudithipudi,et al.  A current-mode CMOS/memristor hybrid implementation of an extreme learning machine , 2014, GLSVLSI '14.

[4]  David Moore,et al.  Silver chalcogenide based memristor devices , 2010, The 2010 International Joint Conference on Neural Networks (IJCNN).

[5]  J. Grollier,et al.  A ferroelectric memristor. , 2012, Nature materials.

[6]  W. Lu,et al.  High-density Crossbar Arrays Based on a Si Memristive System , 2008 .

[7]  Yiran Chen,et al.  Memristor Crossbar-Based Neuromorphic Computing System: A Case Study , 2014, IEEE Transactions on Neural Networks and Learning Systems.

[8]  Frederick T. Chen,et al.  Low-Power and Nanosecond Switching in Robust Hafnium Oxide Resistive Memory With a Thin Ti Cap , 2010, IEEE Electron Device Letters.

[9]  Xinyu Wu,et al.  Energy-efficient STDP-based learning circuits with memristor synapses , 2014, Sensing Technologies + Applications.

[10]  Narayan Srinivasa,et al.  A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. , 2012, Nano letters.

[11]  Andrew S. Cassidy,et al.  A combinational digital logic approach to STDP , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[12]  G. Bi,et al.  Synaptic modification by correlated activity: Hebb's postulate revisited. , 2001, Annual review of neuroscience.

[13]  Karsten Beckmann,et al.  A practical hafnium-oxide memristor model suitable for circuit design and simulation , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[14]  Wei Yang Lu,et al.  Nanoscale memristor device as synapse in neuromorphic systems. , 2010, Nano letters.

[15]  L. Chua.  Memristor-The missing circuit element , 1971 .

[16]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[17]  Kehan Zhu,et al.  A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing , 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

[18]  Hao Jiang,et al.  A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[19]  C. Schneider,et al.  CMOS implementation of analog Hebbian synaptic learning circuits , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

[20]  Yu Wang,et al.  A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Anthony J. Kenyon,et al.  Resistive switching in silicon sub-oxide films , 2012 .

[22]  T. Serrano-Gotarredona,et al.  STDP and STDP variations with memristors for spiking neuromorphic learning systems , 2013, Front. Neurosci..

[23]  Fabien Alibart,et al.  Pattern classification by memristive crossbar circuits using ex situ and in situ training , 2013, Nature Communications.

[24]  Lawrence D. Jackel,et al.  VLSI implementation of a neural network memory with several hundreds of neurons , 1987 .

[25]  Catherine D. Schuman,et al.  An Application Development Platform for neuromorphic computing , 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

[26]  Yong Liu,et al.  A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[27]  Warren Robinett,et al.  Memristor-CMOS hybrid integrated circuits for reconfigurable logic. , 2009, Nano letters.

[28]  Gregory S. Snider,et al.  Spike-timing-dependent learning in memristive nanodevices , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[29]  Jeyavijayan Rajendran,et al.  Leveraging Memristive Systems in the Construction of Digital Logic Circuits , 2012, Proceedings of the IEEE.

[30]  Wofgang Maas,et al.  Networks of spiking neurons: the third generation of neural network models , 1997 .

[31]  Garrett S. Rose,et al.  A synchronized axon hillock neuron for memristive neuromorphic systems , 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

[32]  Richard A. Chapman,et al.  Neural Learning Circuits Utilizing Nano-Crystalline Silicon Transistors and Memristors , 2012, IEEE Transactions on Neural Networks and Learning Systems.

[33]  X. Miao,et al.  Ultrafast Synaptic Events in a Chalcogenide Memristor , 2013, Scientific Reports.

[34]  M. Pickett,et al.  Lognormal switching times for titanium dioxide bipolar memristors: origin and resolution , 2011, Nanotechnology.

[35]  J. Yang,et al.  High switching endurance in TaOx memristive devices , 2010 .

[36]  T. Berzina,et al.  Electrochemical control of the conductivity in an organic memristor: a time-resolved X-ray fluorescence study of ionic drift as a function of the applied voltage. , 2009, ACS applied materials & interfaces.

[37]  Kristy A. Campbell,et al.  Pulse Shape and Timing Dependence on the Spike-Timing Dependent Plasticity Response of Ion-Conducting Memristors as Synapses , 2016, Front. Bioeng. Biotechnol..

[38]  José Luis Huertas,et al.  A CMOS analog adaptive BAM with on-chip learning and weight refreshing , 1993, IEEE Trans. Neural Networks.

[39]  Vinay Kumar,et al.  A software-equivalent SNN hardware using RRAM-array for asynchronous real-time learning , 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

[40]  C. Schneider,et al.  Analog CMOS synaptic learning circuits adapted from invertebrate biology , 1991 .

[41]  Karsten Beckmann,et al.  Techniques for Improved Reliability in Memristive Crossbar PUF Circuits , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[42]  Indranil Saha,et al.  journal homepage: www.elsevier.com/locate/neucom , 2022 .