Methods for reducing memristor crossbar simulation time

Memristor crossbars have the potential to perform parallel resistive computations in the analog domain, and they can be used to develop high density neural network algorithms. However, accurately simulating large memristor crossbars in SPICE (with more than 256 devices) is very difficult and time consuming. This paper discusses using Xyce (a parallel SPICE platform developed by Sandia Labs) to speed up memristor crossbar simulation. Using Xyce, we were able to successfully train neuromorphic memristor crossbars containing 10,096 memristors to learn a large array of linearly separable logic functions. Large memristor crossbars were also used for pattern recognition using both the MNIST and CBCL face datasets. To further reduce training time, a memristor crossbar approximation was simulated in MATLAB. Modeling a crossbar in MATLAB takes significantly less time, but is slightly less accurate. The trained resistance values determined by MATLAB were then downloaded to the more precise crossbar simulated in Xyce (which contains input drivers, comparator circuits, and wire resistance). The classification accuracy found in Xyce was then compared to the accuracy determined when testing the approximated crossbar in MATLAB, as well as a traditional software neural network implementation. To the best of our knowledge, this is the first published result that describes using XYCE to simulate a neuromorphic memristor crossbar using accurate memristor modeling techniques.

[1]  Wei Yang Lu,et al.  Nanoscale memristor device as synapse in neuromorphic systems. , 2010, Nano letters.

[2]  Tarek M. Taha,et al.  Acceleration of hierarchical Bayesian network based cortical models on multicore architectures , 2010, Parallel Comput..

[3]  Mariano Alvira,et al.  MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARTIFICIAL INTELLIGENCE LABORATORY and CENTER FOR BIOLOGICAL AND COMPUTATIONAL LEARNING DEPARTMENT OF BRAIN AND COGNITIVE SCIENCES A.I. Memo No.XXXX C.B.C.L Paper No.XXX An Empirical Comparison of SNoW and SVMs For Face Detection , 2001 .

[4]  Yann LeCun,et al.  The mnist database of handwritten digits , 2005 .

[5]  A.L. Sangiovanni-Vincentelli,et al.  Relaxation-Based Electrical Simulation , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Chris Yakopcic,et al.  Tolerance to defective memristors in a neuromorphic learning circuit , 2014, NAECON 2014 - IEEE National Aerospace and Electronics Conference.

[7]  Eric R. Keiter,et al.  Parallel Transistor-Level Circuit Simulation , 2011 .

[8]  G. Subramanyam,et al.  A Memristor Device Model , 2011, IEEE Electron Device Letters.

[9]  Wei Lu,et al.  Two-terminal resistive switches (memristors) for memory and logic applications , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[10]  Chris Yakopcic,et al.  Exploring the design space of specialized multicore neural processors , 2013, The 2013 International Joint Conference on Neural Networks (IJCNN).

[11]  Andrew S. Cassidy,et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.

[12]  Chris Yakopcic,et al.  SPICE analysis of dense memristor crossbars for low power neuromorphic processor designs , 2015, 2015 National Aerospace and Electronics Conference (NAECON).

[13]  A. Ayatollahi,et al.  Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits , 2009, 2009 European Conference on Circuit Theory and Design.

[14]  Andrew S. Cassidy,et al.  Building block of a programmable neuromorphic substrate: A digital neurosynaptic core , 2012, The 2012 International Joint Conference on Neural Networks (IJCNN).

[15]  Steve B. Furber,et al.  The SpiNNaker Project , 2014, Proceedings of the IEEE.

[16]  Jason Cong,et al.  mrFPGA: A novel FPGA architecture with memristor-based reconfiguration , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[17]  S. Tam,et al.  An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapses , 1990, International 1989 Joint Conference on Neural Networks.

[18]  Chris Yakopcic,et al.  Memristor SPICE Modeling , 2012 .

[19]  Chris Yakopcic,et al.  Efficacy of memristive crossbars for neuromorphic processors , 2014, 2014 International Joint Conference on Neural Networks (IJCNN).