Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET

In this paper, we present the fabrication and electrical characterization of a MOS gated diode based on axially doped silicon nanowire (NW) p-i-n junctions. These nanowires are grown by chemical vapour deposition (CVD) using the vapour–liquid–solid (VLS) mechanism. NWs have a length of about $$7\,\upmu \hbox {m}$$7μm with $$3\,\upmu \hbox {m}$$3μm of doped regions (p-type and n-type) and $$1\,\upmu \hbox {m}$$1μm of intrinsic region. The gate stack is composed of 15 nm of hafnium dioxide ($$\text {HfO}_{2}$$HfO2), 80 nm of nickel and 120 nm of aluminium. At room temperature, $$I_{\text {on}} =-52\,\hbox {nA}/\upmu \hbox {m}\, (V_{\text {DS}}=-0.5\,\text {V}, V_{\text {GS}}=-4\,\text {V})$$Ion=-52nA/μm(VDS=-0.5V,VGS=-4V), and an $$I_{\text {on}}/I_{\text {off}}$$Ion/Ioff ratio of about $$10^{4}$$104 with a very low $$I_{\text {off}}$$Ioff current has been obtained. Electrical measurements are carried out between 90 and 390 K, and we show that the Ion current is less temperature dependent below 250 K. We also observe that the ON current is increasing between 250 and 390 K. These transfer characteristics at low and high temperature confirm the tunnelling transport mechanisms in our devices.

[2]  D. Mariolle,et al.  Dopant profiling in silicon nanowires measured by scanning capacitance microscopy , 2014 .

[3]  Robert H. Dennard,et al.  Practical Strategies for Power-Efficient Computing Technologies , 2010, Proceedings of the IEEE.

[4]  H. Riel,et al.  Toward Nanowire Electronics , 2008, IEEE Transactions on Electron Devices.

[5]  Improved subthreshold characteristics in tunnel field-effect transistors using shallow junction technologies , 2013 .

[6]  J. T. Smith,et al.  Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing , 2011, IEEE Transactions on Electron Devices.

[7]  I. Eisele,et al.  P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths , 2006 .

[8]  S. Sze,et al.  Physics of Semiconductor Devices: Sze/Physics , 2006 .

[9]  Qin Zhang,et al.  Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.

[10]  E. Bertagnolli,et al.  Multimode Silicon Nanowire Transistors , 2014, Nano letters.

[11]  Accelerated Publication: Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires , 2011 .

[12]  Paolo Lugli,et al.  Silicon-nanowire transistors with intruded nickel-silicide contacts. , 2006, Nano letters.

[13]  Cor Claeys,et al.  Temperature impact on the tunnel fet off-state current components , 2012 .

[14]  T. Baron,et al.  Vertically integrated silicon-germanium nanowire field-effect transistor , 2011 .

[15]  S. Trellenkamp,et al.  Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics , 2014 .

[16]  Suman Datta,et al.  Fabrication and characterization of axially doped silicon nanowire tunnel field-effect transistors. , 2010, Nano letters.

[17]  A. Ionescu,et al.  Understanding the Superlinear Onset of Tunnel-FET Output Characteristic , 2012, IEEE Electron Device Letters.

[18]  Walter Riess,et al.  Silicon nanowire tunneling field-effect transistors , 2008 .

[19]  Rita Rooyackers,et al.  Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs , 2012 .

[20]  W. Riess,et al.  Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric , 2011, IEEE Transactions on Electron Devices.

[21]  Qin Zhang,et al.  Can the Interband Tunnel FET Outperform Si CMOS? , 2008, 2008 Device Research Conference.

[22]  Rita Rooyackers,et al.  Drain voltage dependent analytical model of tunnel field-effect transistors , 2011 .

[23]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[24]  H. Riel,et al.  Comparison of VLS grown Si NW tunnel FETs with different gate stacks , 2009, 2009 Proceedings of the European Solid State Device Research Conference.

[25]  J. Knoch,et al.  Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices , 2007 .

[26]  J. Connell,et al.  Spatially resolved correlation of active and total doping concentrations in VLS grown nanowires. , 2013, Nano letters.

[27]  T. Baron,et al.  Effect of HCl on the doping and shape control of silicon nanowires , 2012, Nanotechnology.