A 32 /spl times/ 32 four layer reaction-diffusion CNN chip

This paper describes a 32 /spl times/ 32 four layer neural network chip that exhibits spatially organized patterns of activity, which are formed by reaction-diffusion. The chip was fabricated in 0.5/spl mu/m CMOS n-well process. Measured patterns consist of alternating regions of high and low activity with a preferred width, but no preferred orientation. This chip is an ideal real-time substrate for studying the spatio-temporal dynamics and applications of reaction-diffusion, since it can be characterized experimentally, theoretically and through simulation. It settles to steady state patterns within several hundred microseconds and dissipates 10.45mW.