PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs
暂无分享,去创建一个
Xin Li | Colin C. McAndrew | Weimin Wu | Josef Watts | Gennady Gildenblat | Glen O. Workman | Surya Veeraraghavan | Ronald van Langevelde | Geert D. J. Smit | Andries J. Scholten | Dick B. M. Klaassen | C. McAndrew | D. Klaassen | G. Gildenblat | Weimin Wu | S. Veeraraghavan | G. Workman | G. Smit | A. Scholten | R. V. Langevelde | J. Watts | Xin Li
[1] Tran Ly,et al. Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.
[2] Zhi-Yuan Wu,et al. History-effect-conscious SPICE model extraction for PD-SOI technology , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
[3] L. Esaki,et al. Tunneling in a finite superlattice , 1973 .
[4] R. S. Vogelsong,et al. Simulation of thermal effects in electrical systems , 1989, Proceedings, Fourth Annual IEEE Applied Power Electronics Conference and Exposition.
[5] C.C. McAndrew,et al. Validation of MOSFET model Source–Drain Symmetry , 2006, IEEE Transactions on Electron Devices.
[6] E. Vittoz,et al. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .
[7] G. Gildenblat,et al. Introduction to PSP MOSFET Model , 2005 .
[8] M. Sherony,et al. Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
[9] Xin Li,et al. SP-SOI: a third generation surface potential based compact SOI MOSFET Model , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[10] Carlos Galup-Montoro,et al. An explicit physical model for the long-channel MOS transistor including small-signal parameters , 1995 .
[11] William Redman-White,et al. Impact of self-heating and thermal coupling on analog circuits in SOI CMOS , 1998 .
[12] L. Lemaitre,et al. ADMS-automatic device model synthesizer , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
[13] J. Colinge. Silicon-on-Insulator Technology: Materials to VLSI , 1991 .
[14] R. Rios,et al. A continuous compact MOSFET model for fully- and partially-depleted SOI devices , 1998 .
[15] Samel K. H. Fung,et al. BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs , 2000, Proceedings of the IEEE Custom Integrated Circuits Conference.
[16] G. G. Shahidi. SOI technology for the GHz era , 2002, IBM J. Res. Dev..
[17] R. Puri,et al. Effects of gate-to-body tunneling current on PD/SOI CMOS latches , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..
[18] Jin Cai,et al. Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors , 2001 .
[19] M.M. Pelella,et al. Floating body effects in partially-depleted SOI CMOS circuits , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.
[20] Chenming Hu,et al. Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).
[21] G. Gildenblat,et al. A surface potential-based compact model of n-MOSFET gate-tunneling current , 2004, IEEE Transactions on Electron Devices.
[22] M. Miura-Mattausch,et al. Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects , 2006, IEEE Transactions on Electron Devices.
[23] G. Gildenblat,et al. Benchmarking the PSP Compact Model for MOS Transistors , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.
[24] H.J. Mattausch,et al. HiSIM: a MOSFET model for circuit simulation connecting circuit performance with technology , 2002, Digest. International Electron Devices Meeting,.
[25] G.D.J. Smit,et al. The Physical Background of JUNCAP2 , 2006, IEEE Transactions on Electron Devices.
[26] G. Gildenblat,et al. PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation , 2006, IEEE Transactions on Electron Devices.
[27] G. O. Workman,et al. A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance , 1998 .
[28] G. Gildenblat,et al. SP: an advanced surface-potential-based compact MOSFET model , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[29] C. Hu,et al. Advanced Compact Models for MOSFETs , 2005 .
[30] Kenneth E. Goodson,et al. Measurement and modeling of self-heating in SOI nMOSFET's , 1994 .
[31] F. Klaassen,et al. An explicit surface-potential-based MOSFET model for circuit simulation , 2000 .
[32] G. Gildenblat,et al. A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs , 2007, IEEE Transactions on Electron Devices.