Heading for decananometer CMOS - Is navigation among icebergs still a viable strategy?

Shrinking of dimensions allows new functions, continuous increase in speed, and larger and larger density leading eventually to entire system-onchip integration. For over 30 years this shrinking of devices has being successfully governed by the scaling theory proposed by Denard. The left-hand side of Table I illustrates the scaling theory on an example of 4 passed CMOS generations (between 0.5μm and 0.18μm). The parameter values actually utilized in these technologies correspond to a scaling with factor K=2. The right-hand side of the table shows the predictions of this theory for a medium term (up to 0.07μm) and for a long term (up to 0.025μm). But can the successful scaling continue so far ? The exercise we propose in this paper consists in carrying out an analysis of validity and feasibility of the scaling projections.