Reduction of testing power with pulsed scan flip-flop for scan based testing

In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops (Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using ELDO simulator with TSMC 180 nm CMOS technology. Based on this evaluation, pulsed triggered flip-flop is selected as scan flip-flop because of lower transition power. Comparison of proposed scan flip-flop with existing mux based master-slave scan flip-flop is performed at the layout level. Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.

[1]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[2]  Yu Chien-Cheng.  Design of Low-Power Double Edge-Triggered Flip-Flop Circuit , 2007, 2007 2nd IEEE Conference on Industrial Electronics and Applications.

[3]  Atul K. Jain,et al.  Minimizing power consumption in scan testing: pattern generation and DFT techniques , 2004 .

[4]  Kozo Kinoshita,et al.  On low-capture-power test generation for scan testing , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[5]  Bashir M. Al-Hashimi,et al.  Power-constrained testing of VLSI circuits , 2003 .

[6]  Peiyi Zhao,et al.  Low power and high speed explicit-pulsed flip-flops , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[7]  Arnaud Virazel,et al.  Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles , 2005, VLSI-SoC.

[8]  Mango Chia-Tso Chao,et al.  Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[9]  Manoj Sharma,et al.  An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop , 2009, 2009 International Conference on Advances in Recent Technologies in Communication and Computing.

[10]  Janusz Rajski,et al.  Low Power Scan Shift and Capture in the EDT Environment , 2008, 2008 IEEE International Test Conference.

[11]  Ali Afzali-Kusha,et al.  Low-power single- and double-edge-triggered flip-flops for high-speed applications , 2005 .

[12]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[13]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.