Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example

A methodology for energy-delay optimization of digital circuits is presented. This methodology is applied to minimizing the delay of representative carry-lookahead adders under energy constraints. Impact of various design choices, including the carry-lookahead tree structure and logic style, are analyzed in the energy-delay space and verified through optimization. The result of the optimization is demonstrated on a design of the fastest adder found, a 240-ps Ling sparse domino adder in 1 V, 90 nm CMOS. The optimality of the results is assessed against the impact of technology scaling.

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