ESD protection for RF/AMS ICs: Design and optimization

This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection design optimization and prediction for RF/AMS ICs to ensure 1st Si design success.

[1]  Junjun Li,et al.  Compact modeling of on-chip ESD protection devices using Verilog-A , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  M. Steyaert,et al.  High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection , 2001 .

[3]  Haigang Feng,et al.  A mixed-mode ESD protection circuit simulation-design methodology , 2003 .

[4]  Haigang Feng,et al.  ESD protection design for RF integrated circuits: new challenges , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[5]  Juin J. Liou,et al.  Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Haigang Feng,et al.  ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[7]  Haigang Feng,et al.  ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Haigang Feng,et al.  A review on RF ESD protection design , 2005, IEEE Transactions on Electron Devices.

[9]  Xiao Sun,et al.  Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[10]  Haigang Feng,et al.  A full-monolithic LNA in 0.18/spl mu/m SiGe: performance variation due to ESD protection , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

[11]  Rouying Zhan,et al.  Real 3D electro-thermal simulation and analysis for ESD protection structures , 2004, Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004..

[12]  Qiong Wu,et al.  ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Chun Zhang,et al.  RF Characterization of ESD Protection Structures , 2004, RFIC 2004.

[14]  K. Mayaram,et al.  A packaged 2.4 GHz LNA in a 0.15µm CMOS process with 2kV HBM ESD protection , 2002, Proceedings of the 28th European Solid-State Circuits Conference.