A linearized 1.6–5 GHz low noise amplifier using positive feedback in 65 nm CMOS

A 1.6–5 GHz low noise amplifier has been designed and simulated in a 65 nm CMOS process. The linearity is increased by employing positive feedback using transistors biased in the sub-threshold region. Simulations show that mismatches in the circuit can be neutralized by adjusting the bias point of the feedback transistors. The amplifier has a noise figure below 3 dB, a third order intercept point of +10 dBm, and a voltage gain above 23 dB. In order to obtain a flat gain the amplifier uses a resistive load in combination with current bleeding transistors which give a noise cancelling effect. The circuit consumes 4.9 mA from a 1.5 V supply.

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