Three-Dimensional Integration For Flash Memory Cell

[1]  Y. Iwata,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[2]  G. Nanz,et al.  Modeling of chemical-mechanical polishing: a review , 1995 .

[3]  Betty Prince,et al.  SEMICONDUCTOR MEMORIES , 2006 .

[4]  R. M. Fleming,et al.  Discovery of a useful thin-film dielectric using a composition-spread approach , 1998, Nature.

[5]  R. Ham Handbook of Chemical Vapor Deposition (CVD). Principles, Technology and Applications. Von H. Pierson. Noyes Publications, Park Ridge/New Jersey 1992. 436 S., 69 Abb., 44 Tab., US‐$ 68,– , 1993 .

[6]  L. Klinger,et al.  Kinetics of diffusion growth of silicides in silicon-thin-metal-film systems , 1992 .

[7]  Modeling And Characterization Of Si/SiO/sub 2/ Interface Roughness , 1997, 1997 Symposium on VLSI Technology.

[8]  Shinichi Takagi,et al.  Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique , 2003 .

[9]  Evgeni P. Gusev,et al.  Structure and stability of ultrathin zirconium oxide layers on Si(001) , 2000 .

[10]  S.Y. Lee,et al.  Future 1T1C FRAM technologies for highly reliable, high density FRAM , 2002, Digest. International Electron Devices Meeting,.

[11]  Albert Chin,et al.  Fully Silicided NiSi and Germanided NiGe Dual Gates on SiO 2/Si and Al 2O 3/Ge-On-Insulator MOSFETs , 2003 .

[12]  M. Sakuraba,et al.  Surface Termination of the Ge(100) and Si(100) Surfaces by Using DHF Solution Dipping , 1998 .

[13]  Dim-Lee Kwong,et al.  Fully silicided NiSi and germanided NiGe dual gates on SiO/sub 2//Si and Al/sub 2/O/sub 3//Ge-on-insulator MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[14]  S.Y. Lee,et al.  A process integration of high performance 64 Kb MRAM , 2003, Digest of INTERMAG 2003. International Magnetics Conference (Cat. No.03CH37401).

[15]  Saied N. Tehrani,et al.  Recent developments in magnetic tunnel junction MRAM , 2000 .

[16]  Jyh-Chyurn Guo,et al.  A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistors , 1990 .

[17]  Joseph T. Evans,et al.  Voltage shifts and imprint in ferroelectric capacitors , 1995 .

[18]  J. Gambino,et al.  Silicides and ohmic contacts , 1998 .

[19]  Steven M. George,et al.  Atomic layer controlled deposition of SiO2 and Al2O3 using ABAB… binary reaction sequence chemistry , 1994 .

[20]  Jon M. Slaughter,et al.  Magnetoresistive random access memory using magnetic tunnel junctions , 2003, Proc. IEEE.

[21]  R. D. Schnell,et al.  Surface oxidation states of germanium , 1986 .

[22]  A. Nishiyama,et al.  Direct Comparison of ZrO2 and HfO2 on Ge Substrate in Terms of the Realization of Ultrathin High-κ Gate Stacks , 2004 .

[23]  Z. Benamara,et al.  Preparation and ESCA analysis of the germanium surface: electrical characterization of the Al2O3Ge and Al2O3:GeO2Ge structures , 1994 .

[24]  Dimitri A. Antoniadis,et al.  Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates , 2001 .

[25]  Dim-Lee Kwong,et al.  Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric , 2003, VLSIT 2003.

[26]  James S. Nakos,et al.  Comparison of transformation to low-resistivity phase and agglomeration of TiSi/sub 2/ and CoSi/sub 2/ , 1991 .

[27]  Kevin K. H. Chan,et al.  A Self-Aligned Silicide Process Utilizing Ion Implants for Reduced Silicon Consumption and Control of the Silicide Formation Temperature , 2002 .

[28]  H. Shichijo,et al.  Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon , 1985, IEEE Journal of Solid-State Circuits.

[29]  Kevin K. H. Chan,et al.  A low power 77 K nano-memory with single electron nano-crystal storage , 1995, 1995 53rd Annual Device Research Conference Digest.

[30]  Karlheinz Schwarz,et al.  The interface between silicon and a high-k oxide , 2004, Nature.

[31]  U-In Chung,et al.  An edge contact type cell for Phase Change RAM featuring very low power consumption , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[32]  Zhiguo Meng,et al.  High performance low temperature metal-induced unilaterally crystallized polycrystalline silicon thin film transistors for system-on-panel applications , 2000 .

[33]  D. Kwong,et al.  High quality ultra thin CVD HfO/sub 2/ gate stack with poly-Si gate electrode , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[35]  R. C. Weast CRC Handbook of Chemistry and Physics , 1973 .

[36]  J. Robertson Band offsets of wide-band-gap oxides and implications for future electronic devices , 2000 .

[37]  Y. Iwata,et al.  Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[38]  J. Slaughter,et al.  Progress and outlook for MRAM technology , 1999, IEEE International Magnetics Conference.

[39]  Donggun Park,et al.  A 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size using 90 nm flash technology , 2002, Digest. International Electron Devices Meeting,.

[40]  D. Muller,et al.  Material and electrical characterization of stackable planar polysilicon TFT flash memory cell with metal nanocrystals and high-k dielectrics , 2008, 2008 IEEE International SOI Conference.

[41]  Roberto Bez,et al.  Introduction to flash memory , 2003, Proc. IEEE.

[42]  Kinam Kim,et al.  Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node , 2006, 2006 International Electron Devices Meeting.

[43]  Tsu-Jae King,et al.  Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance , 2003 .

[44]  Eugene A. Fitzgerald,et al.  Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques , 2004 .

[45]  W. Kraus,et al.  A 42.5 mm/sup 2/ 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability , 1998, Seventh Biennial IEEE International Nonvolatile Memory Technology Conference. Proceedings (Cat. No.98EX141).

[46]  A. Pirovano,et al.  Scaling analysis of phase-change memory technology , 2003, IEEE International Electron Devices Meeting 2003.

[47]  R. V. Dover,et al.  Amorphous lanthanide-doped TiOx dielectric films , 1999 .

[48]  T. Jackson,et al.  Gate-self-aligned p-channel germanium MISFETs , 1991, IEEE Electron Device Letters.

[49]  W. M. Haynes CRC Handbook of Chemistry and Physics , 1990 .

[50]  Kinam Kim,et al.  Technology for sub-50nm DRAM and NAND flash manufacturing , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[51]  R. Glang,et al.  Handbook of Thin Film Technology , 1970 .

[52]  R. Wallace,et al.  High-κ gate dielectrics: Current status and materials properties considerations , 2001 .

[53]  D. Muller,et al.  Ni-based self-aligned silicidation (SAS) process on source and drain for planar polysilicon TFT low-voltage flash memory cell , 2009, 2009 Device Research Conference.

[54]  Konstantin K. Likharev,et al.  Layered tunnel barriers for nonvolatile memory devices , 1998 .

[55]  George Rozgonyi,et al.  Morphology and phase stability of TiSi2 on Si , 1992 .

[56]  Jong-Ho Lee,et al.  Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectrics , 1998 .

[57]  S. Lai,et al.  Current status of the phase change memory and its future , 2003, IEEE International Electron Devices Meeting 2003.

[58]  M. Pourbaix Atlas of Electrochemical Equilibria in Aqueous Solutions , 1974 .

[59]  Edwin C. Kan,et al.  Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications , 2005 .

[60]  T. Ma,et al.  High quality ultra-thin (1.5 nm) TiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric for deep sub-micron CMOS technology , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[61]  T. Hou,et al.  Planar polysilicon TFT low-voltage flash memory cell with Al2O3 tunnel dielectric and (Ti,Dy) O control dielectric for three-dimensional integration , 2008, 2008 Device Research Conference.

[62]  T. Fuyuki,et al.  Low Temperature Polycrystalline Silicon Thin Film Transistors Flash Memory with Silicon Nanocrystal Dot , 2007 .

[63]  Trond Ytterdal,et al.  A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects , 1999 .

[64]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[65]  Koeng Su Lim,et al.  Characteristics of silicon nanocrystal floating gate memory using amorphous carbon/SiO2 tunnel barrier , 2002 .

[66]  Dim-Lee Kwong,et al.  Metal nanocrystal memory with high-/spl kappa/ tunneling barrier for improved data retention , 2005 .

[67]  J.C. Lee,et al.  Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[68]  L. Geppert,et al.  The new indelible memories , 2003 .

[69]  Tahone Yang,et al.  A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory , 2006, 2006 International Electron Devices Meeting.

[70]  A. Grill Electrode Structures for Integration of Ferroelectric or High Dielectric Constant Films in Semiconductor Devices , 1998 .

[71]  Robert E. Jones,et al.  Barium Strontium Titanate Capacitors for Embedded Dram , 1998 .

[72]  D. Schlom,et al.  Thermodynamic stability of binary oxides in contact With silicon , 1996 .

[73]  D. Muller,et al.  Materials Characterization of Alternative Gate Dielectrics , 2002 .

[74]  R. Quinn,et al.  Chalcogenide-based non-volatile memory technology , 2001, 2001 IEEE Aerospace Conference Proceedings (Cat. No.01TH8542).

[75]  S. Natarajan,et al.  A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process , 2004, IEEE Journal of Solid-State Circuits.

[76]  K. A. Perry Chemical mechanical polishing: the impact of a new technology on an industry , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[77]  R. Iijima,et al.  Dramatic improvement of Ge p-MOSFET characteristics realized by amorphous zr-silicate/ge gate stack with excellent structural stability through process temperatures , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[78]  T. Hou,et al.  Flash Memory Scaling: From Material Selection to Performance Improvement , 2008 .

[79]  T. Chao,et al.  Nonvolatile Memory Characteristics with Embedded Hemispherical Silicon Nanocrystals , 2007 .

[80]  E. Kan,et al.  Operational and reliability comparison of discrete-storage nonvolatile memories: advantages of single- and double-layer metal nanocrystals , 2003, IEEE International Electron Devices Meeting 2003.

[81]  D. Muller,et al.  The electronic structure at the atomic scale of ultrathin gate oxides , 1999, Nature.

[82]  Kwangseok Han,et al.  Characteristics of p-channel Si nano-crystal memory , 2000 .

[83]  Fumihiko Maeda,et al.  Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces , 2000 .

[84]  S. Sze,et al.  A floating gate and its application to memory devices , 1967 .

[85]  S. Lai,et al.  OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[86]  Saied N. Tehrani,et al.  A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects , 2003, IEEE J. Solid State Circuits.

[87]  R. Ham Handbook of Chemical Vapor Deposition (CVD). Principles, Technology and Applications. (Handbuch der chemischen Dampfabscheidung: Prinzipien, Techniken und Anwendungen). Von H. Pierson, Park Ridge/NJ: Noyes Publications 1992. 436 S., 1993, US‐ $ 68,‐ , 1994 .

[88]  S. P. Murarka,et al.  Refractory silicides for integrated circuits , 1980 .

[89]  Markus Pessa,et al.  atomic layer epitaxy , 1986, Catalysis from A to Z.

[90]  Karen Maex,et al.  Silicides for integrated circuits: TiSi2 CoSi2 , 1993 .

[91]  G. Pei,et al.  Metal nanocrystal memories. I. Device design and fabrication , 2002 .

[92]  L. Colalongo,et al.  Floating body effects in polysilicon thin-film transistors , 1997 .

[93]  Tuo-Hung Hou,et al.  Design Optimization of Metal Nanocrystal Memory—Part I: Nanocrystal Array Engineering , 2006, IEEE Transactions on Electron Devices.

[94]  N. N. Greenwood,et al.  Chemistry of the elements , 1984 .

[95]  A. Tagantsev,et al.  Fatigue of piezoelectric properties in Pb(Zr,Ti)O3 films , 1996 .

[96]  Sandip Tiwari,et al.  Fast and long retention-time nano-crystal memory , 1996 .

[97]  S. M. Sze Physics of semiconductor devices /2nd edition/ , 1981 .

[98]  Shinichi Takagi,et al.  Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction , 2001 .

[99]  T. Hou,et al.  Modeling of Multi-layer Nanocrystal Memory , 2007, 2007 65th Annual Device Research Conference.

[100]  Chul-Hi Han,et al.  A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation , 1999 .

[101]  T. Hiramoto,et al.  Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates , 2002, Digest. International Electron Devices Meeting,.

[102]  R. Finne,et al.  A Water‐Amine‐Complexing Agent System for Etching Silicon , 1967 .

[103]  T. Tezuka,et al.  Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[104]  C. Osburn,et al.  Incorporation of metal silicides and refractory metals in VLSI technology , 1991 .

[105]  E.M. Philofsky FRAM-the ultimate memory , 1996, Proceedings of Nonvolatile Memory Technology Conference.

[106]  J. Woo,et al.  Salicidation process using NiSi and its device application , 1997 .

[107]  J. Plummer,et al.  Modeling of Surrounding Gate MOSFETs With Bulk Trap States , 2007, IEEE Transactions on Electron Devices.

[108]  S. B. Herner,et al.  3D TFT-SONOS memory cell for ultra-high density file storage applications , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[109]  Milton Ohring,et al.  Materials science of thin films : deposition and structure , 2002 .

[110]  Shyam P. Murarka,et al.  Self-aligned silicides or metals for very large scale integrated circuit applications , 1986 .

[111]  H. Nalwa Handbook of thin film materials , 2002 .