Continuous-Time Sigma-Delta for IF

Deep submicron processing, the reduction of the supply voltage as well as the increasing packaging density and the overall low power requirements of integrated circuits and systems raise the demand for novel circuit and design techniques. An important building block of such a mixed-signal system is an analog-to-digital converter (ADC). A multitude of different ADC architectures were introduced over the past decades [1] [2] [3]. The field of application of a particular ADC depends on the achievable conversion speed, accuracy, susceptibility to circuit imperfections, power requirements etc.

[1]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[2]  J. Doernberg,et al.  A 10-bit 5 Msample/sec CMOS 2-step flash ADC , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[3]  Ángel Benito Rodríguez Vázquez,et al.  Fourth-order cascade SC ΣΔ modulators: a comparative study , 1998 .

[4]  J. Doernberg,et al.  A 10-bit 5-Msample/s CMOS two-step flash ADC , 1989 .

[5]  R. Plassche A sigma-delta modulator as an A/D converter , 1978 .

[6]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .

[7]  T.S. Fiez,et al.  A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging , 2000, IEEE Journal of Solid-State Circuits.

[8]  H. Tao,et al.  Analysis of timing jitter in bandpass sigma-delta modulators , 1999 .

[9]  W. Sansen,et al.  A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.

[10]  Yiannos Manoli,et al.  A 1.5V low-power third order continuous-time lowpass ΣΔ A/D converter (poster session) , 2000, ISLPED '00.

[11]  Maurits Ortmanns,et al.  Figure of merit based design strategy for low-power continuous-time /spl Sigma//spl Delta/ modulators , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[12]  Bernhard E. Boser,et al.  The design of sigma-delta modulation analog-to-digital converters , 1988 .

[13]  Michel Steyaert,et al.  Optimal parameters for /spl Delta//spl Sigma/ modulator topologies , 1998 .

[14]  James C. Candy,et al.  A Use of Double Integration in Sigma Delta Modulation , 1985, IEEE Trans. Commun..

[15]  R. T. Baird,et al.  A low oversampling ratio 14-b 500-kHz /spl Delta//spl Sigma/ ADC with a self-calibrated multibit DAC , 1996 .

[16]  Maurits Ortmanns,et al.  On the synthesis of cascaded continuous-time /spl Sigma//spl Delta/ modulators , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[17]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[18]  H. Aboushady,et al.  Jitter effects in continuous-time /spl Sigma//spl Delta/ modulators with delayed return-to-zero feedback , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[19]  G. Temes Delta-sigma data converters , 1994 .

[20]  G. Fischer,et al.  Alternative topologies for sigma-delta modulators-a comparative study , 1997 .

[21]  Belén Pérez-Verdú,et al.  Fourth-order cascade SC /spl Sigma//spl Delta/ modulators: a comparative study , 1998 .

[22]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[23]  Maurits Ortmanns,et al.  A continuous–time sigma–delta modulator with reduced jitter sensitivity , 2002 .

[24]  Michel Steyaert,et al.  A 12-bit intrinsic accuracy high-speed CMOS DAC , 1998, IEEE J. Solid State Circuits.

[25]  W. Martin Snelgrove,et al.  Stability in a general Sigma Delta modulator , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[26]  M. Vertregt,et al.  A 6b 1.6GSample/s flash ADC in 0.18/spl mu/m CMOS using averaging termination , 2002 .

[27]  R. Schreier,et al.  Delta-sigma modulators employing continuous-time circuitry , 1996 .

[28]  Ángel Rodríguez-Vázquez,et al.  Top-Down Design of High-Performance Sigma-Delta Modulators , 1998 .

[29]  R. H. Walden,et al.  A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology , 1995, IEEE J. Solid State Circuits.

[30]  Gabor C. Temes,et al.  Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization , 1996, Proc. IEEE.

[31]  Friedel Gerfers,et al.  A design strategy for low-voltage low-power continuous-time /spl Sigma//spl Delta/ A/D converters , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[32]  Chi-Hung Lin,et al.  Synthesis and analysis of high-order cascaded continuous-time /spl Sigma//spl Delta/ modulators , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[33]  Maurits Ortmanns,et al.  Successful design of cascaded continuous-time /spl Sigma//spl Delta/ modulators , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[34]  Omid Shoaei,et al.  Continuous-Time Delta-Sigma A/D Converters for High Speed Applications , 1995 .