Analysis and comparison on full adder block in submicron technology

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on two classes of circuits, the former with minimum transistor size to minimize power consumption, the latter with optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.35-/spl mu/m process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive. In contrast, the most interesting implementations in terms of trade off between power and delay are the traditional CMOS and mirror topologies. Moreover, the dual-rail domino and the CPL allow the best speed performance.

[1]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[2]  Kenneth W. Martin,et al.  Digital Integrated Circuit Design , 1999 .

[3]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[4]  Tohru Mogami,et al.  A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core , 1997 .

[5]  E. Friedman,et al.  Ramp Input Response of RC Tree Networks , 1996, Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.

[6]  Kazuo Yano,et al.  A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .

[7]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[8]  L. Heller,et al.  Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  David L. Pulfrey,et al.  A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic , 1987 .

[10]  Magdy A. Bayoumi,et al.  Performance evaluation of 1-bit CMOS adder cells , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[11]  Vojin G. Oklobdzija,et al.  Design-performance trade-offs in CMOS-domino logic , 1986 .

[12]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[13]  F. J. Kratochvil A 0.25-μm CMOS 0.9-V 100-MHz DSP Core , 1997 .

[14]  Mohamed I. Elmasry,et al.  Low-Power Digital VLSI Design: Circuits and Systems , 1995 .

[15]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[16]  Mohamed I. Elmasry,et al.  Circuit techniques for CMOS low-power high-performance multipliers , 1996 .

[17]  Yasuhiko Sasaki,et al.  Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.

[18]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[19]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[20]  Akira Matsuzawa Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment , 1994 .

[21]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[22]  Earl E. Swartzlander,et al.  Low Power Arithmetic Components , 1996 .

[23]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[24]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[25]  Tadahiro Kuroda,et al.  Overview of low-power ULSI circuit techniques , 1999 .

[26]  Magdy A. Bayoumi,et al.  A 10-transistor low-power high-speed full adder cell , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[27]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[28]  Earl E. Swartzlander,et al.  Computer Arithmetic , 1980 .

[29]  James B. Kuo,et al.  Low-voltage CMOS VLSI circuits , 1999 .

[30]  Katsuhiro Shimohigashi,et al.  Low-voltage ULSI design , 1993 .

[31]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .