Detection of bridging faults in logic resources of configurable FPGAs using I/sub DDQ/

This paper presents an I/sub DDQ/-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100% coverage of I/sub DDQ/-testable bridging faults. Since reconfiguration programming time can dominate total test time, even with slow I/sub DDQ/ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first, and then to minimize the number of test vectors. 100% coverage for I/sub DDQ/-testable bridging faults is achieved in 5 programming phases and 16 I/sub DDQ/ vectors in the Xilinx XC4000 FPGA family. The RAM modes are tested in a further phase, using 48 test vectors and 38 I/sub DDQ/ measurements.

[1]  Ping Chen,et al.  Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[2]  Fabrizio Lombardi,et al.  An approach for testing programmable/configurable field programmable gate arrays , 1996, Proceedings of 14th VLSI Test Symposium.

[3]  J. Figueras,et al.  I/sub DDQ/ test and diagnosis of CMOS circuits , 1995 .

[4]  Joan Figueras,et al.  IDDQ Test and Diagnosis of CMOS Circuits , 1995, IEEE Design & Test of Computers.

[5]  Xiaotao Chen.  A computer-aided testing framework for field programmable gate arrays: from verification to configuration , 1998 .

[6]  K. El-Ayat,et al.  Array architecture for ATG with 100% fault coverage , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[7]  Fabrizio Lombardi,et al.  Bridging fault detection in FPGA interconnects using IDDQ , 1998, FPGA '98.

[8]  Tong Liu,et al.  Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[9]  Ping Chen,et al.  Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) , 1996, Proceedings of 14th VLSI Test Symposium.

[10]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[11]  J.P. Teixeira,et al.  Back annotation of physical defects into gate-level, realistic faults in digital ICs , 1994, Proceedings., International Test Conference.

[12]  Joan Figueras,et al.  Test of bridging faults in scan-based sequential circuits , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[13]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[14]  H. T. Vierhaus,et al.  Test Generation For Bridging Faults In CMOS ICs Based On Current Monitoring Versus Signal Propagation , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[15]  Bas Verhelst,et al.  Functional and I/sub DDQ/ testing on a static RAM , 1990, Proceedings. International Test Conference 1990.

[16]  Sreejit Chakravarty,et al.  Introduction to ID̳D̳Q̳ testing , 1997 .

[17]  R. Rajsuman,et al.  Iddq testing for CMOS VLSI , 1994, Proceedings of the IEEE.

[18]  Charles F. Hawkins,et al.  IDDQ Testing of VLSI Circuits , 1993, Springer US.

[19]  Wojciech Maly,et al.  Test generation for current testing (CMOS ICs) , 1990, IEEE Design & Test of Computers.

[20]  B. Thomas,et al.  Low cost test solution for IDDQ , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.

[21]  Charles E. Stroud,et al.  Using ILA testing for BIST in FPGAs , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[22]  Manoj Sachdev.  Testing defects in scan chains , 1995 .

[23]  Lan Zhao.  I(DDQ) testing of field programmable gate arrays , 1997 .

[24]  Fabrizio Lombardi,et al.  IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays , 1998, IEEE Trans. Computers.

[25]  Rosa Rodríguez-Montañés,et al.  Analysis of bridging defects in sequential CMOS circuits and their current testability , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[26]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..