IP routing processing with graphic processors
暂无分享,去创建一个
[1] Sotiris Ioannidis,et al. Gnort: High Performance Network Intrusion Detection Using Graphics Processors , 2008, RAID.
[2] Umar Saif,et al. Gigabit routing on a software-exposed tiled-microprocessor , 2005, 2005 Symposium on Architectures for Networking and Communications Systems (ANCS).
[3] George Varghese,et al. Network algorithmics , 2004 .
[4] Laxmi N. Bhuyan,et al. Compiling PCRE to FPGA for accelerating SNORT IDS , 2007, ANCS '07.
[5] Karthikeyan Sankaralingam,et al. Evaluating GPUs for network packet signature matching , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.
[6] Raffaele Bolla,et al. Performance and power consumption modeling for green COTS Software Router , 2009, 2009 First International Communication Systems and Networks and Workshops.
[7] Keith Sklower,et al. A Tree-Based Packet Routing Table for Berkeley Unix , 1991, USENIX Winter.
[8] Fred Kuhns,et al. Supercharging planetlab: a high performance, multi-application, overlay network platform , 2007, SIGCOMM '07.
[9] Myung-Ki Shin,et al. New Challenges on Future Network and Standardization , 2008, 2008 10th International Conference on Advanced Communication Technology.
[10] Laxmi N. Bhuyan,et al. Shared memory multiprocessor architectures for software IP routers , 2003, IEEE Trans. Parallel Distributed Syst..
[11] Katerina J. Argyraki,et al. Can software routers scale? , 2008, PRESTO '08.
[12] Burton H. Bloom,et al. Space/time trade-offs in hash coding with allowable errors , 1970, CACM.
[13] H. Jonathan Chao,et al. High Performance Switches and Routers , 2007 .
[14] M. Crochemore,et al. Algorithms on Strings: Tools , 2007 .
[15] Jeffrey D. Ullman,et al. Introduction to Automata Theory, Languages and Computation , 1979 .
[16] David Waitzman,et al. A 50-Gb/s IP router , 1998, TNET.
[17] Alfred V. Aho,et al. Efficient string matching , 1975, Commun. ACM.
[18] J.B.D. Cabrera,et al. On the statistical distribution of processing times in network intrusion detection , 2004, 2004 43rd IEEE Conference on Decision and Control (CDC) (IEEE Cat. No.04CH37601).
[19] Patrick Crowley,et al. Network Processor Design: Issues and Practices , 2002 .
[20] Edward Fredkin,et al. Trie memory , 1960, Commun. ACM.
[21] EDDIE KOHLER,et al. The click modular router , 2000, TOCS.
[22] D. Manjunath,et al. Control and management plane in a multi-stage software router architecture , 2008, 2008 International Conference on High Performance Switching and Routing.
[23] Hung-Hsiang Jonathan Chao,et al. Next generation routers , 2002, Proc. IEEE.
[24] Kurt Keutzer,et al. Programming challenges in network processor deployment , 2003, CASES '03.
[25] Yangdong Deng,et al. Taming irregular EDA applications on GPUs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[26] Wojciech Maly,et al. 3-Dimensional VLSI - A 2.5-Dimensional integration Scheme , 2010 .
[27] Pavlin Radoslavov,et al. Designing extensible IP router software , 2005, NSDI.
[28] Yuan Xie,et al. Design space exploration for 3D architectures , 2006, JETC.