Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems

This manuscript proposes three classes of codes for error correction in a storage system in which the memory cells do not have the same number of levels, i.e., a multiscale storage. The proposed codes are single multiscale-symbol error correction (SMSEC) codes and are capable of correcting any errors occurring on a single memory cell, namely a column-deleted SMSEC code, an element-compacted SMSEC code and a product SMSEC code. In the proposed codes, the codewords are divided into two partitions, the elements on the first partition are over GF(2b1), while those on the remaining partition are over GF(2b2). This paper also gives guidelines for selection among the three SMSEC codes to meet the desired hardware overhead in the parallel decoder for realistic parameters of the partition pair, such as (b1, b2) 1/4 (4,3), (4,2) and (3,2). Moreover it is shown that the best choice for a MSS system is the SMSEC code with the shortest check bit length; if the check bit lengths of at least two codes are equal, then the use of the element-compacted SMSEC code incurs in the smallest hardware overhead.

[1]  Fabrizio Lombardi,et al.  Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM) , 2015, IEEE Transactions on Computers.

[2]  Yuan Xie,et al.  AdaMS: Adaptive MLC/SLC phase-change memory design for file storage , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[3]  Cecilia Metra,et al.  Error Correcting Strategy for High Speed and High Density Reliable Flash Memories , 2003, J. Electron. Test..

[4]  Chaitali Chakrabarti,et al.  Product Code Schemes for Error Correction in MLC NAND Flash Memories , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  David Hung-Chang Du,et al.  Hybrot: Towards Improved Performance in Hybrid SLC-MLC Devices , 2012, 2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.

[6]  Moinuddin K. Qureshi,et al.  Morphable memory system: a robust architecture for exploiting multi-level phase change memories , 2010, ISCA.

[7]  Stefano Gregori,et al.  An error control code scheme for multilevel Flash memories , 2001, Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing.

[8]  Jongman Kim,et al.  A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems , 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

[9]  Greg Atwood,et al.  Next-Generation Memory [Guest editors' introduction] , 2013, Computer.

[10]  Sungjin Lee,et al.  Improving Performance and Capacity of Flash Storage Devices by Exploiting Heterogeneity of MLC Flash Memory , 2014, IEEE Transactions on Computers.

[11]  Masato Kitakami,et al.  Neighborhood Level Error Control Codes for Multi-Level Cell Flash Memories , 2013, IEICE Trans. Inf. Syst..

[12]  Chaitali Chakrabarti,et al.  Data storage time sensitive ECC schemes for MLC NAND Flash memories , 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

[13]  藤原 英二,et al.  Code design for dependable systems : theory and practical applications , 2006 .

[14]  Jacob Nelson,et al.  Approximate storage in solid-state memories , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[15]  Haralampos Pozidis,et al.  Multilevel phase-change memory , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.