GPS/GLONASS High Dynamic Receiver with Fast Acquisition Engine

For the signal fast acquisition requirement in high dynamic receivers, this paper presents an implementation of a GPS/GLONASS dual mode massively parallel acquisition engine based on FPGA. The engine includes a Partial Matched Filter Banks (PMFB) and a Discrete Fourier Transform (DFT) processor (which is PMFB+DFT) to perform signal full parallel time-frequency two dimensional acquisition. In addition, this engine develops an improved multiple dwell time detector for the signal acquisition, which ensure the high probability of detection and nearly ideal low overall probability of false alarm in a shorter time.