Hardware design of FFT polynomial multipliers

This paper presents the design of two FFT polynomial multipliers using parallel and sequential architectures. Parallel and sequential polynomial multipliers were optimized for throughput and area resources, respectively. The designs are described in generic structural VHDL, synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for high-performance scientific computing applications.

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