Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics

We develop a phenomenological theory of PBTI/TDDB reliability of HK/MG gate stack based on heterogeneous trap generation (TG) and structural relaxation in interfacial (IL) and HK layers. With independently measured parameters, we affirm that for typical HK/MG dielectrics (~1nm IL/3nm HK), significantly higher TG in HK dictates the features of positive bias temperature instability (PBTI) and induces dual-Weibull time dependent dielectric breakdown (TDDB). We also verify that larger relaxation energy in HK suppresses the contribution of HK to the stress induced leakage current (SILC). This framework helps us resolve broad range of puzzling PBTI, TDDB and SILC experiments regarding time evolution, voltage dependence and temperature activation, and establish an intrinsic correlation between SILC performance and PBTI/TDDB degradations in nMOS HK/MG dielectrics. We use this model to explore the trade-off between IL scaling and dielectric reliability, a discussion that will eventually be useful in optimizing the performance-reliability of CMOS technology with HK/MG stack.

[1]  Profiling interface traps in MOS transistors by the DC current-voltage method , 1996, IEEE Electron Device Letters.

[2]  L. Larcher,et al.  Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric , 2008, 2008 IEEE International Electron Devices Meeting.

[3]  S. Mittl,et al.  Positive Bias Temperature Instability Effects in nMOSFETs With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks , 2009, IEEE Transactions on Device and Materials Reliability.

[4]  Jordi Suñé,et al.  Gate stack insulator breakdown when the interface layer thickness is scaled toward zero , 2010 .

[5]  W.L. Chang,et al.  Role of interface layer in stress-induced leakage current in high-k/metal-gate dielectric stacks , 2010, 2010 IEEE International Reliability Physics Symposium.

[6]  Muhammad A. Alam,et al.  A study of soft and hard breakdown - Part I: Analysis of statistical percolation conductance , 2002 .

[7]  Jordi Suñé,et al.  Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides , 2002 .

[8]  Muhammad Ashraful Alam SILC as a Measure of Trap Generation and Predictor of in Ultrathin Oxides , 2002 .

[9]  R. Degraeve,et al.  Experimental identification of unique oxide defect regions by characteristic response of charge pumping , 2011, 2011 International Reliability Physics Symposium.

[10]  R. Degraeve,et al.  Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks , 2008, 2008 IEEE International Electron Devices Meeting.

[11]  G. Bersuker,et al.  Spectroscopic properties of oxygen vacancies in monoclinic HfO2 calculated with periodic and embedded cluster density functional theory , 2007 .

[12]  Mechanistic understanding of Breakdown and Bias Temperature Instability in High-K Metal devices using inline Fast Ramped Bias Test , 2011, 2011 International Reliability Physics Symposium.

[13]  J. Bude,et al.  Gate oxide reliability projection to the sub-2 nm regime , 2000 .

[14]  A. Ghetti,et al.  An anode hole injection percolation model for oxide breakdown-the "doom's day" scenario revisited , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[15]  Guido Groeseneken,et al.  Methodologies for sub-1nm EOT TDDB evaluation , 2011, 2011 International Reliability Physics Symposium.

[16]  S. Takagi,et al.  A new I-V model for stress-induced leakage current including inelastic tunneling , 1999 .

[17]  X. Garros,et al.  PBTI mechanisms in La containing Hf-based oxides assessed by very Fast IV measurements , 2010, 2010 International Electron Devices Meeting.

[18]  M. Alam,et al.  The statistical distribution of percolation resistance as a probe into the mechanics of ultra-thin oxide breakdown , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[19]  K. Banerjee,et al.  Comparison of E and 1/E TDDB models for SiO/sub 2/ under long-term/low-field test conditions , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[20]  Muhammad A. Alam,et al.  SILC as a measure of trap generation and predictor of T/sub BD/ in ultrathin oxides , 2002 .

[21]  SILC-based reassignment of trapping and trap generation regimes of positive bias temperature instability , 2011, 2011 International Reliability Physics Symposium.

[22]  T. Nigam,et al.  TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates , 2009, 2009 IEEE International Reliability Physics Symposium.

[23]  G. Bersuker,et al.  Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application , 2006, 2009 Symposium on VLSI Technology.

[24]  On the defect generation and low voltage extrapolation of Q/sub BD/ in SiO/sub 2//HfO/sub 2/ stacks , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[25]  T. Nigam,et al.  Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks , 2009, 2009 IEEE International Reliability Physics Symposium.

[26]  J. Sune,et al.  Analytical Cell-Based Model for the Breakdown Statistics of Multilayer Insulator Stacks , 2009, IEEE Electron Device Letters.

[27]  L. Larcher,et al.  Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer , 2010, 2010 IEEE International Reliability Physics Symposium.

[28]  H. Shichijo,et al.  off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown , 2007, IEEE Transactions on Electron Devices.

[29]  Dimitris P. Ioannou,et al.  Positive Bias Temperature Instability Effects in nMOSFETs With HfO 2 /TiN Gate Stacks , 2009 .

[30]  Andreas Kerber,et al.  Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress , 2009, 2009 IEEE International Reliability Physics Symposium.

[31]  E. Cartier,et al.  Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks , 2009, IEEE Transactions on Device and Materials Reliability.

[32]  R. Degraeve,et al.  Explaining `Voltage-Driven' Breakdown Statistics by Accurately Modeling Leakage Current Increase in Thin SiON and SiO2/High-K Stacks , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[33]  A. Ghetti,et al.  Field acceleration for oxide breakdown-can an accurate anode hole injection model resolve the E vs. 1/E controversy? , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).