CCD memory using multilevel storage

CCD multilevel storage resulting in increased bit density and decreased sense signal, will be reported, citing design considerations for multilevel storage. Launch and sense circuits which are insensitive to geometry and parameter tolerances will be presented.

[1]  L. Heller.  Cross-coupled charge-transfer sense amplifier , 1979, 1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  L.M. Terman,et al.  Overview of CCD memory , 1976, IEEE Transactions on Electron Devices.

[3]  K. Fujishima,et al.  A new multilevel storage structure for high density CCD memory , 1978, IEEE Journal of Solid-State Circuits.

[4]  R.C. Varshney,et al.  A block organized 64-kbit CCD memory , 1978, IEEE Journal of Solid-State Circuits.

[5]  A.M. Mohsen,et al.  A 64-kbit block addressed charge-coupled memory , 1976, IEEE Journal of Solid-State Circuits.

[6]  S.G. Chamberlain,et al.  Limitations of multilevel storage in charge-coupled devices , 1980, IEEE Transactions on Electron Devices.

[7]  A. Tzou,et al.  A 256K-Bit Charge-Coupled Device Memory , 1980, IBM J. Res. Dev..