Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias

Abstract Three-dimensional (3D) packages utilizing Through Silicon Vias (TSV) are seen as enablers of increased performance and “More than Moore” functionality. However, the use of TSVs introduce a new set of reliability concerns, one of which is the thermo-mechanical stress caused by the mismatch in coefficient of thermal expansion (CTE) between the copper via and the surrounding silicon. The CTE mismatch, causes high stress zones in and around the copper TSVs, which in turn impede the mobility of electrons in the regions surrounding the TSVs. Further, proximal placing of TSVs for improved electrical performance may be restricted by additional stress induced by TSV–TSV interaction. The increased stress of the region surrounding the TSV may also make the dielectric layers more prone to fracture. In order to ensure reliable functioning of 3D chip stacks, design guidelines are necessary on the excluded “keep-out” zone where stress induced by TSVs will impede transistor functionality. Ideally, these design guidelines are based on analytical stress solutions that are easy to incorporate within circuit design tools. Towards this end, we analytically derive, using elasticity theory, the stress field in and around a doubly periodic arrangement of TSVs subjected to a uniform thermal excursion. The solution is then extended to a “coated cylinder” model of TSVs in which the copper via is surrounded by an oxide layer, both of which are included in the silicon matrix. Finally, the model is extended to account for stress reduction caused by the onset of plasticity in the copper via.