BUILT-IN SELF-DIAGNOSTIC READ-ONLY-MEMORIES

The design of built-in self-diagnostic read-only-memories (ROMs) which extends the concept of the built-in self-test to provide fault-masking in the ROM norinal operating mode is presented. Switch-level fault analysis of the ROMs showed that most of the single transistor stuck-openlon faults (on the order of 95% or more) will result in errors confined in the content of a single add,ress. The presented diagnostic scheme identifies these errors and locates the address for which the data are corrupted. 1.n the ROM operating mode the errors are corrected at the ROM outputs when the content of corresponding address is read. A VLSI implementation is presented where the area overhead is estimated to be on the order of 15% or less. 1 @troducticE Read-only-memories (ROMs) are often used for storing the microprograms in the structured controllers of microprocessors. The function of ii control ROM (microcode ROM) is critical to the operation of a processor. To ensure the correct operation, an extensive test procedure for the control ROMs is periodically performed in the off-line mode, and when faults are detected, the microprocessor!j are d:iscarded from the system. The teclhnique tbat will be presented in t:his paper extends the ROMs off-line test procedure to provide fault-masking capabil.ity where the errors appeared at the ROMs outiputs due to internal faults are identified and located in terms of the ROMs add:ress. During the ROM normal operatfton, the errors are corrected at the ROM outputs when the address that has been affected by the fault is read. Since control ROMs are embedded functiional blacks the! proposed testldiagnosis and error-correcting technique will be implemented by means of an additional circuits where the term "built-in self -diagnostic" is used analogous to the built-in self-test (BIST) [1]--[7]. While the scan techniques [5]-[71 can provide access to the test data the amount of time required can -be too great. Alternatively, BIST design eliminates the scan test data, and consequently, achieves the minimal test time. Built-in self-test designs for embedded ROMs, RAMS and PLAs have been proposed in [11-[4], where the techniques are' basically based on exhaustive testing and test response compaction [5][lo]. Zorian and Ivanov [l] has proposed a BIST ROM based on the "Exhaustive Enhanced Output Data Moclif ication," (EEODM) technique which reduces the probability of an error escape due to test response compaction (aliasing probability) compared to techniques based on multiple-input signature register (MISR) [ll], parlty check and check-sum 1.61, 1121. The EEODM scheme uses MISR that can be operated in both directions of shifts to compute the polynomial division of the ROM contents by the feedback polynomial and its reciprocal polynomial , thus, obtain two separate signatures. This scheme also stores the expected quotients resulted from the polynomial division of the contents of the ROM by the feedback polynomial using an additional ROM-array column. The proposed built-in self-diagnostic technique will be based on generalized Hamming codes. These codes had been used for design of single byte error-correcting memories [13], 161 where each memory world is encoded and the errors are concurrently corrected when a word is read. However, for this off-line test/diagnostic scheme, the redundant information of the ROM contents is stored as two additional words as opposed to encoding of each word. The authors has previously applied the generalized Hamming codes for location single faulty chips on the boundary scan boards (141. The weighted check-sum [151 is another scheme that had been proposed for concurrent error-correction in matrix-type computations by array processors. It is suitable €or matrix computation application since the arithmetical operations are available in those array processors. Unfortunately, the attempt to apply the weighted check-sum in the diagnostic technique for the ROMs revealed that the lThis work has been supported by NSF under Grant MIP881348 INTERNATIONAL TEST CONFERENCE 1 9 9 1 CH3032-0/91/0000-00695$01 .OO@ 1991 IEEE Paper 25.4