STUDY OF SRAM AND ITS LOW POWER TECHNIQUES

This paper discusses the basic operations of SRAM such as write, read and hold. These operations are performed with help of tanner tools at .18µm technology. The paper also discusses the low power design techniques for SRAM. There is a four type low power technique discussed here for SRAM. One is the Half-swing Pulse-mode techniques in which a Half-swing Pulse-mode gate family is used that in turn uses reduced input signal swing without sacrificing performance and saves the power. Second is a memory bank partitioning, in which memory array is partitioned to enhance the speed and to reduce the power. Third is the Quiet Bit line architecture in which the voltage of bit line stays as low as possible. To prevent the excessive full-swing charging on the bit line, one-side driving scheme for write operation is used and for read precharge free-pulling scheme is used to keep all bit lines at low voltages at all times. Fourth is the Pulsed Word line and Reduced Bit line Swing in which voltage at bit lines is reduced.