Energy-Efficient Adaptive Computing With Multifunctional Memory
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[1] Norman P. Jouppi,et al. CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.
[2] Cong Xu,et al. Design trade-offs for high density cross-point resistive memory , 2012, ISLPED '12.
[3] Shimeng Yu,et al. Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration , 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[4] Ligang Gao,et al. Programming protocol optimization for analog weight tuning in resistive memories , 2015, 2015 73rd Annual Device Research Conference (DRC).
[5] Cong Xu,et al. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Swarup Bhunia,et al. MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[7] Shimeng Yu,et al. Metal–Oxide RRAM , 2012, Proceedings of the IEEE.
[8] Parthasarathy Ranganathan,et al. From Microprocessors to Nanostores: Rethinking Data-Centric Systems , 2011, Computer.