Design of an Improved and Robust Asynchronous Wrapper ( AW ) for FPGA Applications

Contemporary digital systems must necessarily be based on the “System-on-Chip – SoC” concept. The main reason for that is the need for satisfying the evergrowing demand for higher performance, re-usability and low-power requirements [1,2]. SoC circuits are generally composed by functional modules, which can be IP-cores (intellectual property cores), which are developed by many different vendors. These IP-cores are pre-designed, verified, tested and optimized for highperformance, allowing also cost reduction and shorter development time. However, SoC circuits, when implemented using a global clock signal, are subject to speed and power penalties (clock skew, distribution networks, etc.), leading to a very difficult timing analysis [3]. The need for the implementation of SoC circuits in FPGAs, leads to an even worse clock skew problem, once delays between macro-cells can be very representative. A natural choice for these problems is the asynchronous project methodology [3,6], which can eliminate the previously mentioned challenges by removing the clock signal from the design. But, once they are built with asynchronous modules, some drawbacks can be highlighted focusing on a trustable implementation: a) the lack of reliable tools for asynchronous design; b) difficulties found in hazard-free designing and testing; c) limited culture on asynchronous design; and d) lack of asynchronous IPs [7]. Concerning to asynchronous controllers design in FPGAs [8-9], the drawbacks become even worse, once the internal routing process between macro-cells introduce significant delays that can result in essential-hazard [6]. The more accepted solutions found in literature are related to the circuit class, but the work-around are limited to delay-element insertion, or LUT placement, both solutions presenting difficulties of implementation in commercial FPGAs. AbstrAct1