A methodology for testability enhancement at layout level

In order to make possible the production of cost-effective electronic systems, integrated circuits (ICs) need to be designed for testability. The purpose of this article is to present a methodology for testability enhancement at the lower levels of the design (i.e., at circuit and layout levels). The proposed strategy uses both hardware refinement and software improvement. The main areas of low-cost software improvement are test generation based on a logic description closely related to the physical design, test-vector sequencing, and the introduction of circuit knowledge in fault simulation. The strategy for hardware improvement is based on realistic fault list generation, fault classification (according to fault impact on circuit behavior), and layout-level DFT (design for testability) rules derivation. A preliminary fault classification is proposed, which uncovers the types of realistic faults in MOS digital ICs that are hard to detect, paving the way to derive layout rules for hard-fault avoidance. Simulation examples are presented ascertaining that specific subsets of line-open and bridging faults (according to their topological characteristics) are hard to detect by logic testing using test patterns derived for line stuck-at fault detection.

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