论文信息 - CARIOCA-0.25 /spl mu/m CMOS fast binary front-end for sensor interface using a novel current-mode feedback technique

CARIOCA-0.25 /spl mu/m CMOS fast binary front-end for sensor interface using a novel current-mode feedback technique

We report on a very fast and low noise front-end, implemented in 0.25 /spl mu/m CMOS technology. The CARIOCA amplifier discriminator chip has input impedance of 10 /spl Omega/, in order to be compatible with sensors of large capacitance, and a peaking time of 14 ns. The conversion gain of 8 mV/fC remains almost unchanged up to a detector capacitance of 120 pF. A noise figure of 450e/sup -/ at zero input capacitance with a noise slope of 37.4e/sup -//pF, at a 2.5 V power supply, was measured.

[1] Veljko Radeka,et al. LOW-NOISE TECHNIQUES IN DETECTORS , 1988 .

[2] Federico Faccio,et al. Noise characterization of a CMOS technology for the LHC experiments , 2001 .

[3] P. Jarron,et al. Integrated circuits for particle physics experiments , 2000, IEEE Journal of Solid-State Circuits.

[4] Georges Charpak,et al. The Use of Multiwire Proportional Counters to Select and Localize Charged Particles , 1968 .

[5] A. Marchioro,et al. Analog design in deep submicron CMOS processes for LHC , 1999 .

[6] Ruth H. Pater,et al. Nuclear Instruments and Methods in Physics Research. Section B; Microstructural Characterization of Semi-Interpenetrating Polymer Networks by Positron Lifetime Spectroscopy , 1998 .

[7] Federico Faccio,et al. Deep submicron CMOS technologies for the LHC experiments , 1999 .

[8] Federico Faccio,et al. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects , 1999 .