Cumulative Differential Nonlinearity Testing of ADCs

This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 212 samples, which can only be achieved with 222 samples using the conventional method. It only needs 16 registers to store code bins in this experiment. key words: cumulative differential nonlinearity, gain error, jitter calibration, analog-to-digital converters (ADCs)

[1]  Seung-Hoon Lee,et al.  A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  L. Satish,et al.  ADC Static Characterization Using Nonlinear Ramp Signal , 2010, IEEE Transactions on Instrumentation and Measurement.

[3]  Ieee Std,et al.  IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters , 2011 .

[4]  Chun-Cheng Huang,et al.  A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques , 2011, IEEE Journal of Solid-State Circuits.

[5]  Minho Kwon,et al.  A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[6]  Abhijit Chatterjee,et al.  A high-resolution jitter measurement technique using ADC sampling , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[7]  J. Blair.  Histogram measurement of ADC nonlinearities using sine waves , 1994 .

[8]  Degang Chen,et al.  Accurate testing of analog-to-digital converters using low linearity signals with stimulus error identification and removal , 2005, IEEE Transactions on Instrumentation and Measurement.

[9]  L. Satish,et al.  ADC Static Nonlinearity Estimation Using Linearity Property of Sinewave , 2011, IEEE Transactions on Instrumentation and Measurement.

[10]  Tetsuya Matsumoto,et al.  A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture , 2010, IEEE Journal of Solid-State Circuits.

[11]  Francisco André Corrêa Alegria,et al.  Standard Histogram Test Precision of ADC Gain and Offset Error Estimation , 2007, IEEE Transactions on Instrumentation and Measurement.

[12]  Pasquale Daponte,et al.  Performance analysis of an ADC histogram test using small triangular waves , 2002, IEEE Trans. Instrum. Meas..

[13]  Dario Petri,et al.  Stochastic properties of quantization noise in memoryless converters affected by integral nonlinearity , 2004, IEEE Transactions on Instrumentation and Measurement.

[14]  Hsin-Wen Ting,et al.  A Histogram-Based Testing Method for Estimating A/D Converter Performance , 2008, IEEE Transactions on Instrumentation and Measurement.

[15]  Dario Petri,et al.  Noise sensitivity of the ADC histogram test , 1998, IEEE Trans. Instrum. Meas..

[16]  Cecilia Metra,et al.  Low-area on-chip circuit for jitter measurement in a phase-locked loop , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[17]  Yuji Gendai,et al.  The Maximum-Likelihood Noise Magnitude Estimation in ADC Linearity Measurements , 2010, IEEE Transactions on Instrumentation and Measurement.

[18]  Minho Kwon,et al.  A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture , 2011, IEEE Journal of Solid-State Circuits.

[19]  Daniel Bloyet,et al.  Measurement of timing jitter contributions in a dynamic test setup for A/D converters , 2001, IEEE Trans. Instrum. Meas..