SEE test and modeling results on 45nm SRAMs with different well strategies

This paper presents heavy ion experimental results on SRAMs processed with 45nm bulk technology. Experiments were analyzed for Multiple Cells Upset (MCU) occurrence. The tested device was especially designed for MCU studies. In order to limit their spread it embeds different well strategies: usage of triple well layer and several densities of well ties.

[1]  Robert Ecoffet,et al.  SEU response of an entire SRAM cell simulated as one contiguous three dimensional device domain , 1998 .

[2]  R. Harboe-Sorensen,et al.  High penetration heavy tons at the RADEF test site , 2003, Proceedings of the 7th European Conference on Radiation and Its Effects on Components and Systems, 2003. RADECS 2003..

[3]  G. Gasiot,et al.  Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering , 2007, IEEE Transactions on Nuclear Science.

[4]  R. Harboe-Sorensen,et al.  Heavy ion testing and 3D simulations of Multiple Cell Upset in 65nm standard SRAMs , 2007, 2007 9th European Conference on Radiation and Its Effects on Components and Systems.