A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS) based on quarter-wave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.

[1]  J. Lahti,et al.  A digital frequency modulator circuit for a dual-mode cellular telephone , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[2]  J. Holmes,et al.  A Second-Order All-Digital Phase-Locked Loop , 1974, IEEE Trans. Commun..

[3]  Trevor J. Terrell.  Introduction to Digital Filters , 1980 .

[4]  H. Samueli,et al.  A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance , 1991 .

[5]  Sergio Bampi,et al.  Design of a digital FM demodulator based on a 2nd° order all-digital phase-locked loop , 2007, SBCCI '07.

[6]  Donald R. Stephens.  Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations , 2001 .

[7]  A.M. Fahim,et al.  Low-power direct digital frequency synthesis for wireless communications , 2000, IEEE Journal of Solid-State Circuits.

[8]  Jalil Fadavi-Ardekani.  M×N Booth encoded multiplier generator using optimized Wallace trees , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[9]  H. Samueli,et al.  An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation , 1987, 41st Annual Symposium on Frequency Control.

[10]  Wonyong Sung,et al.  A CORDIC-based digital quadrature mixer: comparison with a ROM-based architecture , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[11]  Markku Renfors,et al.  Area-optimized FPGA implementation of a digital FM modulator , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[12]  Venceslav F. Kroupa.  Methods of Mapping from Phase to Sine Amplitude in Direct Digital Synthesis , 1999 .

[13]  G. Venkatesh,et al.  Techniques for low power realization of FIR filters , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[14]  Jalil Fadavi-Ardekani,et al.  M*N Booth encoded multiplier generator using optimized Wallace trees , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[15]  Ki-seon Cho,et al.  54x54-bit radix-4 multiplier based on modified booth algorithm , 2003, GLSVLSI '03.

[16]  Tughrul Arslan,et al.  Low power multiplication scheme for FIR filter implementation on single multiplier CMOS DSP processors , 1996 .

[17]  Noel Boutin,et al.  An arctangent type wideband PM/FM demodulator with improved performance , 1992 .

[18]  V. S. Reinhardt,et al.  Sine output DDSs. A survey of the state of the art , 1998, Proceedings of the 1998 IEEE International Frequency Control Symposium (Cat. No.98CH36165).

[19]  Bang-Sup Song,et al.  A digital FM demodulator for FM, TV, and wireless , 1995 .

[20]  C. J. Kikkert,et al.  Investigation into the effects of quantisation noise on a digital FM modulator , 1996, Proceedings of Digital Processing Applications (TENCON '96).

[21]  Katsuhiko Ogata,et al.  Modern Control Engineering , 1970 .

[22]  C. R. Cole,et al.  CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications , 1984 .

[23]  Fubing Yu.  FPGA implementation of a fully digital FM demodulator , 2004, The Ninth International Conference onCommunications Systems, 2004. ICCS 2004..

[24]  Mary Jane Irwin,et al.  Area-time-power tradeoffs in parallel adders , 1996 .

[25]  Z. Sauli,et al.  An efficient Modified Booth multiplier architecture , 2008, 2008 International Conference on Electronic Design.

[26]  S. Gupta,et al.  The Digital Phase-Locked Loop as a Near-Optimum FM Demodulator , 1972, IEEE Trans. Commun..

[27]  Francisco Cardells-Tormo,et al.  Optimized FPGA-implementation of quadrature DDS , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[28]  B. Gold,et al.  A digital frequency synthesizer , 1971 .

[29]  G. Pasternack,et al.  Analysis and synthesis of a digital phase-locked loop for FM demodulation , 1968 .

[30]  John G. Proakis,et al.  Digital signal processing (3rd ed.): principles, algorithms, and applications , 1996 .

[31]  C. J. Kikkert,et al.  Performance of a digital stereo FM modulator with reduced output resolution , 1997 .

[32]  Marimuthu Palaniswami,et al.  A fast-multiplier generator for FPGAs , 1995, Proceedings of the 8th International Conference on VLSI Design.

[33]  Hsin-Lei Lin,et al.  Design of a novel radix-4 booth multiplier , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..