A 1.5 V high-linearity CMOS mixer for 2.4 GHz applications

A folded-cascode mixer with a modified class-AB transconductor for 2.4 GHz ISM band applications is presented in this paper. The mixer is composed of a modified class-AB transconductor and a low-voltage design technique. The proposed architecture improves the performance of linearity in the RF front-end. Simulation results for the proposed mixer using TSMC 0.8 /spl mu/m mixed signal CMOS process are: input 1-dB compression point (P -1dB) -1.15 dBm, input third-order intercept point (IIP3) 11 dBm, power conversion gain 1 dB, and single side-band noise figure 17.3 dB. The mixer consumes 5.86 mA of current from a 1.5 V power supply.

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