Physics-based simulation of single-event effects
暂无分享,去创建一个
[1] Lloyd W. Massengill,et al. Analysis of the influence of MOS device geometry on predicted SEU cross sections , 1999 .
[2] R. Koga,et al. Single Event Error Immune CMOS RAM , 1982, IEEE Transactions on Nuclear Science.
[3] P. T. McDonald,et al. Practical approach to ion track energy distribution , 1988 .
[4] Kody Varahramyan,et al. Three-dimensional modeling and evaluation of body tied versus floating body SOI MOSFETs , 1999 .
[5] Lloyd W. Massengill,et al. Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .
[6] H. T. Weaver,et al. Two-Dimensional Simulation of Single Event Indujced Bipolar Current in CMOS Structures , 1984, IEEE Transactions on Nuclear Science.
[7] Olaf Schenk,et al. The effects of unsymmetric matrix permutations and scalings in semiconductor device and circuit simulation , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] N. Ghoniem,et al. The Size Effect of Ion Charge Tracks on Single Event Multiple-Bit Upset , 1987, IEEE Transactions on Nuclear Science.
[9] Robert A. Reed,et al. Charge collection spectroscopy , 1993 .
[10] Edward M. Buturla,et al. Finite-element analysis of semiconductor devices: The FIELDAY program , 1981, IBM Journal of Research and Development.
[11] D. Binder,et al. Satellite Anomalies from Galactic Cosmic Rays , 1975, IEEE Transactions on Nuclear Science.
[12] Larry D. Edmonds. A time-dependent charge-collection efficiency for diffusion , 2001 .
[13] Frédéric Wrobel,et al. Incidence of multi-particle events on soft error rates caused by n-Si nuclear reactions , 2000 .
[14] James E. Turner,et al. Heavy-Ion Track Structure in Silicon , 1979, IEEE Transactions on Nuclear Science.
[15] Marty R. Shaneyfelt,et al. Charge collection and SEU from angled ion strikes , 1997 .
[16] C. L. Axness,et al. Mechanisms Leading to Single Event Upset , 1986, IEEE Transactions on Nuclear Science.
[17] J. Ziegler. THE STOPPING AND RANGE OF IONS IN SOLIDS , 1988 .
[18] Marty R. Shaneyfelt,et al. Impact of technology trends on SEU in CMOS SRAMs , 1996 .
[19] V. Ferlet-Cavrois,et al. Comparison of the sensitivity to heavy ions of SRAM's in different SIMOX technologies , 1994, IEEE Electron Device Letters.
[20] Changhong Dai,et al. Impact of CMOS process scaling and SOI on the soft error rates of logic processes , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
[21] Daniel M. Fleetwood,et al. Implementing QML for radiation hardness assurance , 1990 .
[22] C. Detcheverry,et al. SEU critical charge and sensitive area in a submicron CMOS technology , 1997 .
[23] H. T. Weaver. Soft error stability of p-well versus n-well CMOS latches derived from 2-D transient simulations , 1988, Technical Digest., International Electron Devices Meeting.
[24] P. Dodd,et al. Production and propagation of single-event transients in high-speed digital logic ICs , 2004, IEEE Transactions on Nuclear Science.
[25] Robert B. Hammond,et al. An Approach to Measure Ultrafast-Funneling-Current Transients , 1986, IEEE Transactions on Nuclear Science.
[26] B. D. Shafer,et al. The design of radiation-hardened ICs for space: a compendium of approaches , 1988, Proc. IEEE.
[27] E. Petersen,et al. Soft Errors Due to Protons in the Radiation Belt , 1981, IEEE Transactions on Nuclear Science.
[28] D. D. Tang,et al. A circuit concept for reducing soft-error in high-speed memory cells , 1987, 1987 Symposium on VLSI Circuits.
[29] H.T. Weaver,et al. RAM cell recovery mechanisms following high-energy ion strikes , 1987, IEEE Electron Device Letters.
[30] F. W. Sexton,et al. Microbeam studies of single-event effects , 1996 .
[31] P. Dodd,et al. Various SEU conditions in SRAM studied by 3-D device simulation , 2001 .
[32] M. Baze,et al. Comparison of error rates in combinational and sequential logic , 1997 .
[33] G. E. Davis,et al. Transient Radiation Effects in SOI Memories , 1985, IEEE Transactions on Nuclear Science.
[34] P. Dodd,et al. Radiation effects in SOI technologies , 2003 .
[35] Hideyuki Iwata,et al. Numerical analysis of alpha-particle-induced soft errors in SOI MOS devices , 1992 .
[36] J. Choma,et al. Single Event Upset in SOS Integrated Circuits , 1987, IEEE Transactions on Nuclear Science.
[37] J. Ziegler,et al. stopping and range of ions in solids , 1985 .
[38] J. L. Wirth,et al. The Analysis of Radiation Effects in Semiconductor Junction Devices , 1967 .
[39] Y. Yagil,et al. A systematic approach to SER estimation and solutions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[40] A. B. Campbell,et al. Alpha-, boron-, silicon- and iron-ion-induced current transients in low-capacitance silicon and GaAs diodes , 1988 .
[41] M. R. Pinto,et al. The effects of ion track structure in simulating single event phenomena , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).
[42] D. S. Walsh,et al. SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments , 2001 .
[43] Marty R. Shaneyfelt,et al. Impact of substrate thickness on single-event effects in integrated circuits , 2001 .
[44] Sherra E. Diehl,et al. An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMS , 1986, IEEE Transactions on Nuclear Science.
[45] Allan H. Johnston,et al. The influence of VLSI technology evolution on radiation-induced latchup in space systems , 1996 .
[46] M. R. Pinto,et al. Numerical simulation of heavy ion charge generation and collection dynamics , 1993 .
[47] O. Flament,et al. Study of transient current induced by heavy-ion in NMOS/SOI transistors , 2002 .
[48] O. Fageeha,et al. Distribution of radial energy deposition around the track of energetic charged particles in silicon , 1994 .
[49] Kartikeya Mayaram,et al. Transient three-dimensional mixed-level circuit and device simulation: algorithms and applications , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[50] Mark R. Pinto,et al. Device Simulation for Silicon ULSI , 1991 .
[51] R. R. O'Brien,et al. Dynamics of Charge Collection from Alpha-Particle Tracks in Integrated Circuits , 1981, 19th International Reliability Physics Symposium.
[52] M. Lundstrom. Fundamentals of carrier transport , 1990 .
[53] A. B. Campbell,et al. Comparison of experimental charge collection waveforms with PISCES calculations , 1991 .
[54] R. R. O'Brien,et al. Collection of charge from alpha-particle tracks in silicon devices , 1983, IEEE Transactions on Electron Devices.
[55] H. L. Grubin,et al. Simulation of Charge Collection in a Multilayer Device , 1985, IEEE Transactions on Nuclear Science.
[56] O. Musseau. Single-event effects in SOI technologies and devices , 1996 .
[57] Robert Ecoffet,et al. SEE results using high energy ions , 1995 .
[58] D. S. Walsh,et al. Single-event upset and snapback in silicon-on-insulator devices and integrated circuits , 2000 .
[59] S. P. Buchner,et al. Laboratory tests for single-event effects , 1996 .
[60] R. L. Woodruff,et al. Three-dimensional numerical simulation of single event upset of an SRAM cell , 1993 .
[61] R. J. McPartland. Circuit simulations of alpha-particle-induced soft errors in MOS dynamic RAMs , 1981 .
[62] R. R. O'Brien,et al. A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices , 1981, IEEE Electron Device Letters.
[63] G. L. Hash,et al. Impact of ion energy on single-event upset , 1998 .
[64] H. T. Weaver,et al. Comparison of 2D Memory SEU Transport Simulation with Experiments , 1985, IEEE Transactions on Nuclear Science.
[65] Paul E. Dodd,et al. Device simulation of charge collection and single-event upset , 1996 .
[66] Jr. Leonard R. Rockett. Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors , 1992 .
[67] T. Toyabe,et al. The scaling law of alpha-particle induced soft errors for VLSI's , 1986, 1986 International Electron Devices Meeting.
[68] H. L. Grubin,et al. Numerical simulation of charge collection in two- and three-dimensional silicon diodes—a comparison , 1986 .
[69] W. A. Kolasinski,et al. Cost-effective numerical simulation of SEU , 1988 .
[70] L. Tosti,et al. Charge enhancement effect in NMOS bulk transistors induced by heavy ion Irradiation-comparison with SOI , 2004, IEEE Transactions on Nuclear Science.
[71] Ping Yang,et al. SIERRA: a 3-D device simulator for reliability modeling , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[72] S. Selberherr. Analysis and simulation of semiconductor devices , 1984 .
[73] M. Xapsos. Applicability of LET to single events in microelectronic structures , 1992 .
[74] Wojtek Hajdas,et al. Low energy proton induced SEE in memories , 1997 .
[75] A. E. Waskiewicz,et al. Experimental and simulation study of the effects of cosmic particles on CMOS/SOS RAMs , 1990 .
[76] R. Koga,et al. Scaling studies of CMOS SRAM soft-error tolerances—From 16K to 256K , 1987, 1987 International Electron Devices Meeting.
[77] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[78] Robert Katz,et al. The radial distribution of dose around the path of a heavy ion in liquid water , 1986 .
[79] J. C. Pickel,et al. Rate prediction for single event effects-a critique , 1992 .
[80] Stephen LaLumondiere,et al. Correlation of picosecond laser-induced latchup and energetic particle-induced latchup in CMOS test structures , 1995 .
[81] R. Koga,et al. Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, 64 K*1 NMOS SRAMs , 1988 .
[82] W. R. Eisenstadt,et al. CMOS VLSI single event transient characterization , 1989 .
[83] John Choma,et al. Mixed-mode PISCES-SPICE coupled circuit and device solver , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[84] John R. Hauser,et al. Simulation Approach for Modeling Single Event Upsets on Advanced CMOS SRAMS , 1985, IEEE Transactions on Nuclear Science.
[85] R. Dennard,et al. Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon , 2000 .
[86] F. W. Sexton,et al. Critical charge concepts for CMOS SRAMs , 1995 .
[87] Robert Katz,et al. An analytic representation of the radial distribution of dose from energetic heavy ions in water, Si, LiF, NaI, and SiO2 , 1990 .
[88] Kartikeya Mayaram,et al. Algorithms for transient three-dimensional mixed-level circuit and device simulation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[89] J. Pelloie,et al. Laser probing of bipolar amplification in 0.25-/spl mu/m MOS/SOI transistors , 2000 .
[90] Dipen N. Sinha,et al. Transient Measurements of Ultrafast Charge Collection in Semicouductor Diodes , 1987, IEEE Transactions on Nuclear Science.
[91] R. Koga,et al. Numerical Simulation of SEU Induced Latch-Up , 1986, IEEE Transactions on Nuclear Science.
[92] H. Saito,et al. SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design , 2002 .
[93] J. S. Browning,et al. Processing Enhanced SEU Tolerance in High Density SRAMs , 1987, IEEE Transactions on Nuclear Science.
[94] Gernot Heiser,et al. Three-dimensional numerical semiconductor device simulation: algorithms, architectures, results , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[95] Lloyd W. Massengill,et al. Single event mirroring and DRAM sense amplifier designs for improved single-event-upset performance , 1994 .
[96] Lloyd W. Massengill,et al. A proposed SEU tolerant dynamic random access memory (DRAM) cell , 1994 .
[97] Robert Katz,et al. Energy Deposition by Electron Beams and δ Rays , 1968 .
[98] P. S. Winokur,et al. Three-dimensional simulation of charge collection and multiple-bit upset in Si devices , 1994 .
[99] Jack A. Mandelman,et al. The use of simulation in semiconductor technology development , 1990 .
[100] Lloyd W. Massengill,et al. Effects of process parameter distributions and ion strike locations on SEU cross-section data (CMOS SRAMs) , 1993 .
[101] Robert Ecoffet,et al. SEU response of an entire SRAM cell simulated as one contiguous three dimensional device domain , 1998 .
[102] B. D. Shafer,et al. Considerations for Single Event Immune VLSI Logic , 1983, IEEE Transactions on Nuclear Science.
[103] J. A. Zoutendyk,et al. Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification , 1987, IEEE Transactions on Nuclear Science.
[104] Larry D. Edmonds,et al. Electric currents through ion tracks in silicon devices , 1998 .
[105] H.T. Weaver,et al. Memory SEU simulations using 2-D transport calculations , 1985, IEEE Electron Device Letters.
[106] H. Saito,et al. Analysis of body-tie effects on SEU resistance of advanced FD-SOI SRAMs through mixed-mode 3-D Simulations , 2004, IEEE Transactions on Nuclear Science.
[107] John A. Zoutendyk,et al. Investigation of single-event upset (SEU) in an advanced bipolar process , 1988 .
[108] P. Eaton,et al. Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[109] R. Koga,et al. SEU characterization of hardened CMOS SRAMs using statistical analysis of feedback delay in memory cells , 1989 .
[110] J.A. Seitchik,et al. Single event charge collection modeling in CMOS multi-junctions structure , 1986, 1986 International Electron Devices Meeting.