PACE2: an improved parallel VLSI extractor with parameter extraction

An algorithm, PACE2, is described which is targeted to the second phase of extraction, called the parameter extraction phase. The authors have interfaced two models for resistance and capacitance. They propose a different partitioning scheme, namely, by equal number of rectangles, so as to balance the load. The parallel algorithm has been implemented on the Intel iPSC2/D4-MX hypercube.<<ETX>>