A mixed-signal decision-feedback equalizer that uses a look-ahead architecture
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[1] Bernard Widrow,et al. Adaptive Signal Processing , 1985 .
[2] Jan W. M. Bergmans. Density improvements in digital magnetic recording by decision feedback equalization , 1986 .
[3] Christer Svensson,et al. A true single-phase-clock dynamic CMOS circuit technique , 1987 .
[4] Jieh-Tsorng Wu,et al. A 100-MHz pipelined CMOS comparator , 1988 .
[5] Fuyun Ling,et al. The LMS algorithm with delayed coefficient adaptation , 1989, IEEE Trans. Acoust. Speech Signal Process..
[6] Charles G. Sodini,et al. A 200-MHz CMOS phase-locked loop with dual phase detectors , 1989 .
[7] C.M. Melas,et al. Adaptive equalization in magnetic-disk storage channels , 1990, IEEE Communications Magazine.
[8] Keshab K. Parhi. Pipelining in algorithms with quantizer loops , 1991 .
[9] John M. Cioffi,et al. An adaptive RAM-DFE for storage channels , 1991, IEEE Trans. Commun..
[10] Paul J. Hurst,et al. Design of an analog DFE for disk-drive applications , 1992, [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers.
[11] G. A. De Veirman,et al. Design of a bipolar 10-MHz programmable continuous-time 0.05 degrees equiripple linear phase filter , 1992 .
[12] R. R. Spencer,et al. An analog discrete-time transversal filter in 2.0 mu m CMOS , 1992, [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers.
[13] A.A. Abidi,et al. A discrete-time analog signal processor for disk read channels , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[14] George S. Moschytz,et al. Adaptive switched-capacitor filters based on the LMS algorithm , 1993 .
[15] William A. Sethares,et al. Weak convergence and local stability properties of fixed step size recursive algorithms , 1993, IEEE Trans. Inf. Theory.
[16] T. W. Matthews,et al. An integrated analog CMOS Viterbi detector for digital magnetic recording , 1993 .
[17] Robert Andrew Kertis,et al. A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection , 1993 .
[18] Stephen H. Lewis,et al. A switched-capacitor differencing circuit with common-mode rejection for fully differential comparators , 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.
[19] Iskender Agi,et al. A comparison of analog DFE architectures for disk-drive applications , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[20] D. Browning,et al. A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[21] Trent Dudley,et al. Implementation of a Digital Reamrite Channel with EEPR4 Detection , 1995 .
[22] David A. Johns,et al. Comparison of DC offset effects in four LMS adaptive algorithms , 1995 .
[23] K. Nagaraj,et al. A high speed, low power PRML read channel device , 1995 .
[24] R. R. Spencer,et al. Analog timing recovery architectures for PRML detectors , 1995, Proceedings of GLOBECOM '95.
[25] Stephen H. Lewis,et al. A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure , 1995 .
[26] Inkyu Lee,et al. Performance evaluation of an adaptive RAM-DFE read channel , 1995 .
[27] P.J. Hurst,et al. Adaptive continuous-time forward equalization for DFE-based disk-drive read channels , 1995, Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers.
[28] R. R. Spencer,et al. Comparison of different detection techniques for digital magnetic recording channels , 1995 .
[29] Asad A. Abidi,et al. A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels , 1996 .
[30] J. Kovacs,et al. Hybrid phase locked loop system for PRML disk drive read channels , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.
[31] G.T. Uehara,et al. A 200 MHz 9-tap analog equalizer for magnetic disk read channels in 0.6 /spl mu/m CMOS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[32] Paul J. Hurst,et al. A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-/spl mu/m CMOS , 1996 .
[33] K. Parsi,et al. A 200 Mb/s PRML read/write channel IC , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[34] R. Dakshinamurthy,et al. A 200 Mb/s analog DFE read channel , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.