Design of Efficient Reversible Binary Comparator

In recent years, research in reversible logic has attracted significance attention leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose Design of Efficient Reversible Binary Comparator. The input circuit and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator are designed using input circuit as first stage and one-bit comparator cell as second stage and so on. The Power consumption, Delay, Garbage outputs and Constant inputs are computed. It is observed that the Quantum cost and Garbage output values are less in the proposed technique compared to the existing approaches.